Single-transistor EEPROM array and operation methods

A method comprising:

• performing an operation on an electrically erasable programmable read-only memory (EEPROM) array, wherein the operation is selected from a program operation or an erase operation, and wherein the EEPROM array comprises:
• EEPROM cells arranged in rows and columns;
• a plurality of word-lines extending in a column direction, wherein each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column;
• a plurality of drain-lines extending in the column direction, wherein each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, and wherein none of the plurality of drain-lines is shared by neighboring columns of the EEPROM cells;
• and
• a plurality of source-lines extending in a row direction, wherein each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row, wherein during the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage lower than the first source-line voltage.

A method comprising:

• performing a program operation on an electrically erasable programmable read-only memory (EEPROM) array, the step of performing the program operation comprising:
• applying a positive voltage to a source of a selected cell in the EEPROM array;
• and
• applying a zero or a negative voltage to a drain of a selected cell.