Nonvolatile memory device

A nonvolatile memory device, comprising:

• a page buffer unit, comprising page buffers arranged in a form of a matrix and coupled to I/O line pairs corresponding to respective page buffer rows, wherein each of the page buffers is coupled to one or more of bit lines to which memory cells are coupled through a sense node and configured to couple each of the I/O line pairs and a latch circuit for outputting data together in response to an operation mode or to select one I/O line of the I/O line pair and to couple the selected I/O line and the sense node;
• a Y decoder unit, comprising first to Nth decoders coupled to respective N page buffer columns of the page buffer unit and each configured to output a first or a second control signal in response to address signals and first and second operation mode selection signals, where Nth corresponds to a column of the page buffer unit;
• a mode selection unit outputting the first and second operation selection signals for selecting the operation mode;
• and
• an I/O control unit, comprising I/O control circuits coupled to the I/O line pairs, respectively, and each configured to detect data inputted and output through each of the I/O line pairs and output the detected data or to couple one of the first or second I/O lines to a data line.