Two word line SRAM cell with strong-side word line boost for write provided by weak-side word line

Abstract

An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle.

Dependencies are inferred from the claim text.