US 8,300,446 B2Granted

Ferroelectric random access memory with single plate line pulse during read

AssigneeTexas Instruments Incorporated

InventorSaim Ahmad Qidwai

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Abstract

A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.

Claims19

Dependent claims

A method of operating a ferroelectric memory to read a stored data state from a selected memory cell, the memory cell having a ferroelectric capacitor with first and second plates, and a pass transistor connected between the second plate of the capacitor and a bit line, the ferroelectric capacitor capable of being polarized into first and second data states, the method comprising the steps of:

precharging the bit line associated with the selected memory cell;
energizing a word line connected to the gate of the pass transistor to cause conduction between the second plate of the ferroelectric capacitor and the bit line;
performing a charge transfer operation during the energizing step by applying a boost voltage to the first plate of the ferroelectric capacitor of the selected memory cell;
then sensing the stored data state of the selected memory cell from the bit line occurring responsive to the step of performing the charge transfer operation;
then performing a single write-back during the energizing step, responsive to the stored data state being the second data state, by applying a voltage to the bit line associated with the selected memory cell, the voltage sufficient so that a differential voltage between that bit line and the first plate of the selected memory cell exceeds a coercive voltage of the ferroelectric capacitor corresponding to the second data state;
and
then de-energizing the word line.

4 more elements

A method of operating a ferroelectric memory to read a stored data state from a selected memory cell, the memory cell having a ferroelectric capacitor comprising a first plate coupled to a plate line associated with a row containing the memory cell, a second plate, and ferroelectric material disposed between the first and second plates, wherein the capacitor is polarized to a first data state by a positive voltage greater than a first coercive voltage being applied across the first and second plates, and wherein the capacitor is polarized to a second data state by a negative voltage of a magnitude greater than a second coercive voltage being applied across the first and second plates, the method comprising the steps of:

precharging a bit line associated with the selected memory cell;
then selectively coupling, responsive to a row address, the second plate of the capacitor of the selected memory cell to the bit line;
during the selectively coupling step, applying a plate line boost voltage to the first plate of the ferroelectric capacitor of the selected memory cell sufficient that, if the stored data state of the selected memory cell is the first data state, a differential voltage between the first plate and the bit line associated with the selected memory cell exceeds the first coercive voltage of the capacitor;
then sensing the stored data state of the selected memory cell from the bit line;
then, responsive to the stored data state being a second data state, applying a write voltage to the bit line associated with the selected memory cell sufficient that a differential voltage between that bit line and the first plate of the selected memory cell exceeds the second coercive voltage of the ferroelectric capacitor;
and
then terminating the coupling step.

4 more elements

A non-volatile memory, comprising:

a plurality of memory cells arranged in rows and columns, each memory cell comprising:
a capacitor having a first plate coupled to a plate line associated with a row containing the memory cell, having a second plate, and having ferroelectric material disposed between the first and second plates, wherein the capacitor is polarized to a first data state by a positive voltage greater than a first coercive voltage being applied across the first and second plates, and wherein the capacitor is polarized to a second data state by a negative voltage of a magnitude greater than a second coercive voltage being applied across the first and second plates;
a pass transistor having a source/drain path connected between the second plate of the capacitor and a bit line associated with a column containing the memory cell, and having a gate coupled to a word line associated with the row containing the memory cell;
a plurality of sense amplifiers, each coupled to one of a plurality of bit lines;
write circuitry, coupled to the plurality of bit lines;
an address decoder, biased from a power supply voltage, coupled to a plurality of word lines, and coupled to receive a row portion of a received address;
plate line driver circuitry, for applying selected voltages to one or more of a plurality of plate lines in each memory access cycle;
voltage boost circuitry, coupled to the plate line driver circuitry, for generating a boost voltage to the plate line driver circuitry, so that, during a read cycle, the plate line driver circuitry applies a plate line boost voltage to the second plate of the ferroelectric capacitor of memory cells in a selected row, the plate line boost voltage sufficient that, if the stored data state of a selected memory cell is the first data state, a differential voltage between the first plate and the bit line associated with the selected memory cells exceeds the first coercive voltage of the capacitor for that memory cell.

5 more elements

Dependencies are inferred from the claim text.