Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHiroyuki Nagashima, Koichi Kubo, Yasuyuki Fukuda
Life of this patent
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Abstract
A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.
Claims15
A nonvolatile semiconductor memory device, comprising:
- a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in a matrix, each memory cell using a variable resistor;
- a pulse generator operative to generate plural types of write pulses for varying the resistance of said variable resistor based on write data;
- a selection circuit operative to apply write pulses generated by said pulse generator to one of said memory cells;
- a sense amplifier operative to execute verify read to said memory cell;
- a status decision circuit operative to decide a verify result based on an output from said sense amplifier;
- and
- a control circuit operative to execute additional write to said memory cell based on said verify result from said status decision circuit,
- wherein said sense amplifier executes verify read to plural memory cells in batch, and
- wherein said control circuit makes the verify result pass if a number of bits with the verify result indicative of fail is not more than a number of pre-determined allowable failed bits.
A nonvolatile semiconductor memory device, comprising:
- a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in a matrix, each memory cell using a variable resistor;
- a pulse generator operative to generate plural types of write pulses for varying a resistance of said variable resistor in three or more stages based on ternary or higher valued write data;
- a selection circuit operative to apply write pulses generated by said pulse generator to one of said memory cells;
- a sense amplifier operative to execute verify read to said memory cell;
- a status decision circuit operative to decide a verify result based on an output from said sense amplifier;
- and
- a control circuit operative to execute additional write to said memory cell based on said verify result from said status decision circuit,
- wherein said selection circuit executes write to plural of said memory cells simultaneously,
- wherein said sense amplifier sets plural verify levels corresponding to the resistances of said variable resistor in three or more stages and executes verify read to plural of said memory cells in batch based on said plural verify levels, and
- wherein said control circuits executes said additional write to said memory cells with said verify result indicative of fail.
A nonvolatile semiconductor memory device, comprising:
- a memory cell array including a cell array of electrically erasable programmable nonvolatile memory cells arranged in a matrix and an ECC (Error Correction Code) area, each memory cell using a variable resistor;
- a pulse generator operative to generate plural types of write pulses for varying the resistance of said variable resistor based on write data;
- a selection circuit operative to apply write pulses generated by said pulse generator to one of said memory cells;
- a sense amplifier operative to execute verify read to said memory cell;
- a status decision circuit operative to decide whether a verify result falls within an ECC relievable range based on an output from said sense amplifier;
- and
- a control circuit operative to execute additional write to said memory cell based on said verify result from said status decision circuit,
- wherein said sense amplifier executes verify read to plural memory cells in batch, and
- wherein said control circuit makes the verify result pass if a number of bits with the verify result indicative of fail is not more than a number of pre-determined allowable failed bits.
Dependencies are inferred from the claim text.