US 8,300,342 B2Granted

Multi-bit phase alignment for synchronization mark pattern matching

AssigneeHGST Netherlands B.V.

InventorsRichard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Todd Carter Truax

Life of this patent

Estimating the term…

Loading patent…

Abstract

Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.

Claims17

Dependent claims

A method of detecting a synchronization mark, the method comprising:

reading a stream of bits from a storage medium, wherein the stream of bits is read as output from a matched filter upstream of a primary data detector;
performing pattern matching to determine whether a pattern of bits read from the storage medium, matches at least a portion of a synchronization mark;
recognizing in the stream of bits, a phase of a repeated pattern of N bits indicative of a synchronization field;
performing phase alignment to determine whether a location of the first bit of the pattern, is consistent with an expected location of the synchronization mark based upon the phase;
wherein the phase alignment is performed by comparing a number of the first bit with a modulo N counter reading;
wherein N=4;
wherein the phase alignment indicates the synchronization mark if, the phase is 0 and the reading of the modulo counter 4 is zero, the phase is 1 and the reading of the modulo 4 counter is zero, the phase is 1 and the reading of the modulo 4 counter is 1, the phase is 2 and the reading of modulo 4 counter is 2, or the phase is 3 and the reading of the modulo 4 counter is 3;
and
indicating an existence of a synchronization mark only where the pattern matching and phase alignment are satisfied.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/150,814Filed 30 Apr 2008
Published: US 2009/0274028 A15 Nov 2009
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11B 20/10009
Digital recording or reproducing: improvement or modification of read or write signals
G11B 20/10027
Analog processing for digital recording or reproduction: adjusting the signal strength during recording or reproduction, e.g. variable gain amplifiers
G11B 20/10046
Improvement or modification of read or write signals: filtering or equalising, e.g. setting the tap weights of an FIR filter
G11B 20/10055
Filtering or equalising, e.g. setting the tap weights of an FIR filter: using partial response filtering when writing the signal to the medium or…