Gate drive circuit having at least three clock signals and having forward and reverse driving modes and driving method thereof

A driving method of a gate driving circuit, the gate driving circuit comprising a plurality of cascaded drive units sequentially outputting an output signal, the driving method comprising the steps of:

• inputting a plurality of clock signals in a sequence into the gate driving circuit;
• inputting a scan start signal or a scan end signal into a first-stage cascaded drive unit of the gate driving circuit;
• inputting the scan end signal or the scan start signal into a last-stage cascaded drive unit of the gate driving circuit;
• and
• reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal thereby reversing a driving direction of the gate driving circuit;
• wherein each of the cascaded drive units comprises:
• a first switch, comprising a control terminal receiving a first clock signal, a first terminal receiving a first input signal, and a second terminal coupled to a node;
• a second switch, comprising a control terminal receiving a second clock signal, a first terminal coupled to the node, and a second terminal receiving a second input signal;
• and
• a third switch, comprising a control terminal coupled to the node, a first terminal receiving a third clock signal, and a second terminal outputting the output signal;
• wherein the first input signal and the second input signal are output signals of cascaded drive units adjacent to an nth cascaded drive unit, and the first clock signal, the third clock signal and the second clock signal are three successive clock signals following a sequence of first, third and second clock signals.