Demultiplexer drive circuit

A demultiplexer drive circuit used in a liquid crystal display having a plurality of pixels, wherein the pixels are arranged into multiple pixel rows and each of the pixel rows receives a first scan clock signal and a second scan clock signal, the demultiplexer drive circuit writing pixel data transmitted from a same data line into different pixels in a time-division manner, and comprising:

• a first switching device connected to the first scan clock signal from a first gate line and the second scan clock signal from a second gate line;
• a second switching device, its control terminal being connected to the first switching device and the rest of its terminals being connected to the data line and a first pixel electrode;
• a third switching device, its control terminal being connected to the first switching device and the rest of its terminals being connected to the data line and a second pixel electrode;
• a fourth switching device connected to the first scan clock signal from the first gate line and the second scan clock signal from the second gate line and its control terminal being connected to the third switching device;
• and
• a fifth switching device, its control terminal being connected to the fourth switching device and the rest of its terminals being connected to the data line and a third pixel electrode;
• wherein the first scan clock signal and the second scan clock signal have a substantially identical pulse width and a phase difference of substantially half of the pulse width.