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US 8,299,982 B2Granted
Emission control line driver and organic light emitting display using the emission control line driver
AssigneeSamsung Display Co., Ltd.
InventorBo Yong Chung
Life of this patent
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Abstract
An emission control line driver capable of being mounted on a panel, of improving driving speed, and of minimizing power consumption. The emission control line driver includes stage circuits each having clock, inverted clock, and start pulse inputs and each generating an emission control signal pulse. The stage circuits are cascaded to provide a series of emission control signals.
Claims25
An emission control line driver configured to receive first and second clock signals and inverted first and inverted second clock signals, the emission control line driver comprising:
- a plurality of stages, each stage configured to receive one of the first and second clock signals and one of an inverted first clock signal and an inverted second clock signal, wherein each stage comprises first and second output transistors, wherein the first and second output transistors are electrically connected to an output of the stage and are connected to first and second power supplies, respectively, wherein the plurality of stages comprises:
- a first stage comprising first and second clock inputs, the first and second clock inputs configured to receive the first clock signal, and a third clock input, the third clock input configured to receive the inverted first clock signal;
- a second stage comprising fourth and fifth clock inputs, the fourth and fifth clock inputs configured to receive the second clock signal, and a sixth clock input, the sixth clock input configured to receive the inverted second clock signal;
- a third stage comprising seventh and eighth clock inputs, the seventh and eighth clock inputs configured to receive the inverted first clock signal, and a ninth clock input, the ninth clock input configured to receive the first clock signal;
- and
- a fourth stage comprising tenth and eleventh clock inputs, the tenth and eleventh clock inputs configured to receive the inverted second clock signal, and a twelfth clock input, the twelfth clock input configured to receive the second clock signal,
- wherein each of the first, second, third, and fourth stages comprises:
- an input unit, the input unit configured to supply a first signal to a first node, and
- an output unit configured to output an emission control signal corresponding to the first signal, and
- wherein the input unit comprises:
- a first transistor, the first transistor electrically connected between a first power source and the first node, wherein the gate electrode of the first transistor is electrically connected to one of the first clock input, fourth clock input, seventh clock input and tenth clock input,
- a second transistor, the second transistor electrically connected to the first node and electrically connected to one of the third clock input, sixth clock input, ninth clock input and twelfth clock input,
- a first capacitor, the first capacitor electrically connected between a gate electrode of the second transistor and the first node, and
- a third transistor, the third transistor electrically connected to the gate electrode of the second transistor by a conductor contacting both the third transistor and the gate electrode of the second transistor, and electrically connected to one of the second clock input, fifth clock input, eighth clock input and eleventh clock input, wherein the third transistor is configured to receive a start signal and to transmit the start signal to the second transistor,
- wherein the clock input electrically connected to the gate electrode of the first transistor is electrically connected to the clock input electrically connected to the third transistor, wherein the first transistor is configured to selectively electrically connect the first node to the first power source according to the clock signal of the clock input electrically connected to the gate electrode of the first transistor.
12 more elements
An organic light emitting display comprising
- a pixel portion comprising a plurality of pixels electrically connected to a plurality of emission control lines, a plurality of scan lines, and a plurality of data lines,
- a scan driver configured to drive the scan lines;
- a data driver configured to drive the data lines;
- and
- an emission control line driver configured to supply emission control signals to the emission control lines, wherein the emission control line driver comprises:
- a first stage comprising first and second clock inputs, the first and second clock inputs configured to receive a first clock signal, and a third clock input, the third clock input configured to receive an inverted first clock signal;
- a second stage comprising fourth and fifth clock inputs, the fourth and fifth clock inputs configured to receive a second clock signal, and a sixth clock input, the sixth clock input configured to receive an inverted second clock signal;
- a third stage comprising seventh and eighth clock inputs, the seventh and eighth clock inputs configured to receive the inverted first clock signal, and a ninth clock input, the ninth clock input configured to receive the first clock signal;
- and
- a fourth stage comprising tenth and eleventh clock inputs, the tenth and eleventh clock inputs configured to receive the inverted second clock signal, and a twelfth clock input, the twelfth clock input configured to receive the second clock signal,
- wherein each of the first, second, third, and fourth stages comprises:
- first and second output transistors, wherein the first and second output transistors are electrically connected to an output of the stage and are connected to first and second power supplies, respectively,
- an input unit, the input unit configured to supply a first signal to a first node, and
- an output unit configured to output an emission control signal corresponding to the first signal, and
- wherein the input unit comprises:
- a first transistor, the first transistor electrically connected between a first power source and the first node, wherein the gate electrode of the first transistor is electrically connected to one of the first clock input, fourth clock input, seventh clock input and tenth clock input,
- a second transistor, the second transistor electrically connected to the first node and electrically connected to one of the third clock input, sixth clock input, ninth clock input and twelfth clock input,
- a first capacitor, the first capacitor electrically connected between a gate electrode of the second transistor and the first node, and
- a third transistor, the third transistor electrically connected to the gate electrode of the second transistor by a conductor contacting both the third transistor and the gate electrode of the second transistor, and electrically connected to one of the second clock input, fifth clock input, eighth clock input and eleventh clock input, wherein the third transistor is configured to receive a start signal and to transmit the start signal to the second transistor,
- wherein the clock input electrically connected to the gate electrode of the first transistor is electrically connected to the clock input electrically connected to the third transistor, wherein the first transistor is configured to selectively electrically connect the first node to the first power source according to the clock signal of the clock input electrically connected to the gate electrode of the first transistor.
17 more elements
A control signal driving circuit configured to provide a control signal pulse substantially aligned with a clock input signal, wherein the control signal pulse is provided in response to a start pulse input signal, the circuit comprising:
- a capacitor;
- first and second output transistors, wherein the capacitor and the first and second output transistors are electrically connected to an output and the first and second output transistors are electrically connected to first and second power supplies, respectively;
- an input unit, the input unit configured to supply a first signal to a first node, and
- an output unit configured to output an emission control signal corresponding to the first signal,
- wherein the input unit comprises:
- a first transistor, the first transistor electrically connected between a first power source and the first node, wherein the gate electrode of the first transistor is electrically connected to one of the first clock input, fourth clock input, seventh clock input and tenth clock input,
- a second transistor, the second transistor electrically connected to the first node and electrically connected to one of the third clock input, sixth clock input, ninth clock input and twelfth clock input,
- a first capacitor, the first capacitor electrically connected between a gate electrode of the second transistor and the first node, and
- a third transistor, the third transistor electrically connected to the gate electrode of the second transistor, by a conductor contacting both the third transistor and the gate electrode of the second transistor, and electrically connected to one of the second clock input, fifth clock input, eighth clock input and eleventh clock input, wherein the third transistor is configured to receive a start signal and to transmit the start signal to the second transistor,
- wherein the clock input electrically connected to the gate electrode of the first transistor is electrically connected to the clock input electrically connected to the third transistor, wherein the first transistor is configured to selectively electrically connect the first node to the first power source according to the clock signal of the clock input electrically connected to the gate electrode of the first transistor.
7 more elements
A control signal driving circuit configured to provide a control signal pulse substantially aligned with a clock input signal, wherein the control signal pulse is provided in response to a start pulse input signal, the circuit comprising:
- means for generating a single pulse substantially aligned with the clock input signal, wherein the single pulse is provided in response to a start pulse input signal;
- and
- means for generating the control signal pulse, wherein the control signal pulse is an inverted version of the single pulse, the generating means being electrically connected to first and second power supplies,
- wherein each of the means for generating the single pulse comprises:
- an input unit, the input unit configured to supply a first signal to a first node, and
- an output unit configured to output an emission control signal corresponding to the first signal, and
- wherein the input unit comprises:
- a first transistor, the first transistor electrically connected between a first power source and the first node, wherein the gate electrode of the first transistor is electrically connected to one of the first clock input, fourth clock input, seventh clock input and tenth clock input,
- a second transistor, the second transistor electrically connected to the first node and electrically connected to one of the third clock input, sixth clock input, ninth clock input and twelfth clock input,
- a first capacitor, the first capacitor electrically connected between a gate electrode of the second transistor and the first node, and
- a third transistor, the third transistor electrically connected to the gate electrode of the second transistor by a conductor contacting both the third transistor and the gate electrode of the second transistor, and electrically connected to one of the second clock input, fifth clock input, eighth clock input and eleventh clock input, wherein the third transistor is configured to receive a start signal and to transmit the start signal to the second transistor,
- wherein the clock input electrically connected to the gate electrode of the first transistor is electrically connected to the clock input electrically connected to the third transistor, wherein the first transistor is configured to selectively electrically connect the first node to the first power source according to the clock signal of the clock input electrically connected to the gate electrode of the first transistor.
9 more elements
Dependencies are inferred from the claim text.