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US 8,299,847 B2Granted
Semiconductor device and data processing system including the same
AssigneeElpida Memory, Inc.
InventorTatsuya Matano
Life of this patent
Estimating the term…
Abstract
A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy power lines. Fourth, third, sixth, and fifth potentials of the second, third, fifth, and sixth dummy power lines satisfy fourth potential<third potential<first potential, and sixth potential>fifth potential>second potential. With this configuration, a leakage current flowing between a substrate and a gate of a transistor that becomes on at the time of standby, and a leakage current flowing between the substrate and a drain of a transistor that becomes off at the time of standby can be reduced.
Claims22
A semiconductor device comprising:
- first and fourth power lines that are not power gated;
- second, third, fifth and sixth power lines that are power gated;
- a first logic circuit having an input node to receive an input signal and an output node to output an output signal, one power node on a high potential side and other power node on a low potential side, the one power node of the first logic circuit being connected to the third power line, and the other power node of the first logic circuit being connected to the fifth power line;
- a second logic circuit having an input node to receive an input signal and an output node to output an output signal, one power node on a high potential side and other power node on a low potential side, the one power node of the second logic circuit being connected to the second power line, and the other power node of the second logic circuit being connected to the sixth power line;
- and
- a control circuit that performs power gating control over the second, third, fifth and sixth power lines, respectively, wherein
- the control circuit controls, in a first state, an electric potential of the second and third power lines to a first potential of the first power line and controls an electric potential of the fifth and sixth power lines to a second potential of the fourth power line,
- the control circuit further controls, in a second state, an electric potential of the third power line to a third potential lower than the first potential, an electric potential of the second power line to a fourth potential lower than the third potential, an electric potential of the sixth power line to a fifth potential higher than the second potential, and an electric potential of the fifth power line to a sixth potential higher than the fifth potential,
- the first logic circuit outputs a signal having the third potential from the output node thereof in the second state, and
- the second logic circuit outputs a signal having the fifth potential from the output node thereof in the second state.
7 more elements
A semiconductor device comprising:
- first to third power lines respectively supplied with an electric potentials showing a first logical level;
- a fourth power line supplied with an electric potential showing a second logical level;
- a first off-leakage control circuit that supplies the second power line with an electric potential that is same as the first potential of the first power line by electrically connecting the second power line to the first power line in a first state, and electrically disconnects the second power line from the first power line in a second state;
- a second off-leakage control circuit that supplies the third power line with an electric potential that is same as the first potential in the first state, and supplies the third power line with a third potential shifted from the first potential toward a second potential lower than the first potential of the fourth power line in the second state;
- and
- a circuit block including a plurality of logic circuits each having an output node, wherein
- the circuit block includes first logic circuits which a signal output from the output node thereof in the second state is fixed to the first logical level, each of the first logic circuits includes one power node connected to the third power line and other power node supplied with the second potential at least in the first state, and
- the circuit block includes second logic circuits which a signal output from the output node thereof in the second state is fixed to the second logical level, each of the second logic circuits includes one power node connected to the second power line and other power node supplied with the second potential at least in the first state.
5 more elements
A semiconductor device comprising:
- a first logic circuit having a first output node and including a first transistor of a first conductivity type that becomes electrically conductive when an output signal to be output from the first output node to a high level and a second transistor of a second conductivity type that becomes electrically conductive when the output signal to be output from the first output node to a low level;
- and
- a second logic circuit having a second output node and including a third transistor of the first conductivity type that becomes electrically conductive when an output signal to be output from the second output node to a high level and a fourth transistor of the second conductivity type that becomes electrically conductive when the output signal to be output from the second output node to a low level, wherein
- in a first state
- an electric potential of drains of the first to fourth transistors that is in an electrical conductive state becomes a first potential when an output signal of a corresponding logic circuit is at a high level and becomes a second potential when an output signal of a corresponding logic circuit is at a low level,
- in a second state
- an electric potential of a drain of the first transistor becomes a third potential shifted from the first potential toward the second potential,
- a voltage between a source and a drain of the second transistor becomes smaller than a difference potential between the third potential and the second potential,
- an electric potential of a drain of the fourth transistor becomes a fifth potential shifted from the second potential toward the first potential,
- a voltage between a source and a drain of the third transistor becomes smaller than a difference potential between the first potential and the fifth potential, and
- absolute potentials are higher in order of the first potential, the third potential, the fifth potential, and the second potential.
8 more elements
Dependencies are inferred from the claim text.