Internal voltage generating circuit of semiconductor device

An internal voltage generating circuit of a semiconductor device, comprising:

• a voltage level detecting unit configured to detect a level of an internal voltage terminal, based on a target level, and generate a first driving control pulse having an activation period varying according to the detection result;
• a first driver configured to pull up the internal voltage terminal in response to the first driving control pulse;
• a frequency detecting unit configured to receive and detect a frequency of an external clock and generate a periodic driving control signal having a predefined active pulse width in each period of periods of the periodic driving control signal, wherein the periods of the periodic driving control signal vary in response to the frequency of the external clock and the predefined activation pulse width remains the same in response to variations in the frequency of the external clock;
• and
• a second driver configured to pull up the internal voltage terminal in response to the periodic driving control signal, regardless of a level variation of the voltage level of the internal voltage terminal.

An internal voltage generating circuit of a semiconductor device, comprising:

• a first voltage driver configured to compare an internal voltage terminal with a reference voltage to pull up the internal voltage terminal during a period where a level of the internal voltage terminal is lower than the reference voltage;
• and
• a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock CLK, regardless of a level variation of the voltage level of the internal voltage terminal,
• wherein the second voltage driver comprises:
• a frequency detecting unit configured to detect the frequency of the external clock and generate a periodic driving control signal having a predefined activation period in each period varying according to the detection result;
• and
• a first driving unit configured to pull up the internal voltage terminal in response to the periodic driving control signal,
• wherein the frequency detecting unit comprises:
• a buffer configured to buffer the external clock in response to an operation control signal:
• a frequency divider configured to divide an output clock of the buffer by a predefined multiple;
• and
• a detection pulse generator configured to generate the periodic driving control signal having the predefined activation period at each edge of a clock output from the frequency divider.