Capacitively and conductively coupled multiplexer

A multiplexer, comprising:

• N input nodes configured to receive input signals on input signal paths, wherein a given input node is configured to receive a given input signal on a given input signal path;
• nonlinear capacitors, wherein a given nonlinear capacitor is coupled to the given input node, wherein the given nonlinear capacitor has a first capacitance, which is less than a threshold, in a non-selected state, and a second capacitance, which is greater than the threshold, in a selected state;
• and wherein the given nonlinear capacitor includes a metal-oxide-semiconductor (MOS) transistor that includes a gate, a drain, and a source;
• an output node, coupled to the nonlinear capacitors, configured to provide an output signal on an output signal path;
• control logic configured to provide at least one control signal to switch a state of at least one of the nonlinear capacitors to the selected state, thereby providing AC coupling for at least one of the input signals to the output node;
• an amplifier coupled to the nonlinear capacitors and the output node;
• and
• selection circuits, wherein inputs of a given selection circuit are coupled to the given input node and the control logic, wherein an output of the given selection circuit is coupled to the given nonlinear capacitor, and wherein the selection circuits include static NAND gates, dynamic NAND gates, static NOR gates, or dynamic NOR gates.

A method for multiplexing at least one input signal to an output node;

• receiving at least the one input signal on at least one of N input nodes;
• providing, using one or more selection circuits and control logic, at least one control signal to switch a state of at least one nonlinear capacitor, which is coupled to at least the one of the N input nodes, to a selected state, thereby providing AC for coupling at least the one input signal to the output node;
• and
• amplifying a signal on the output node using an amplifier that is coupled to the at least one nonlinear capacitor and the output node,
• wherein at least the one nonlinear capacitor has a first capacitance, which is less than a threshold, in a non-selected state, and a second capacitance, which is greater than the threshold, in the selected state, and wherein the at least one nonlinear capacitor includes a metal-oxide-semiconductor (MOS) transistor that includes a gate, a drain, and a source,
• wherein inputs of a given selection circuit are coupled to the given input node and the control logic, wherein an output of the given selection circuit is coupled to the given nonlinear capacitor and wherein the selection circuits include static NAND gates, dynamic NAND gates, static NOR gates, or dynamic NOR gates.