Clock generation circuit, semiconductor device including the same, and method of generating clock signal

A semiconductor device having a clock generation circuit, the clock generation circuit comprising:

• a delay line that delays a first clock signal to generate a second clock signal;
• a counter circuit that specifies an amount of delay of the delay line based on a count value thereof;
• a counter control circuit that adjusts the count value of the counter circuit so that first active edges of the first and second clock signals have a predetermined relationship;
• and
• a duty adjustment circuit that adjusts a second active edge of the second clock signal based on first and second count values at each of which the first active edges of the first and second clock signals have the predetermined relationship.

A semiconductor device comprising:

• a clock generation circuit;
• an output buffer that outputs output data to outside in synchronization with a second clock signal;
• and
• a replica buffer that is a replica of the output buffer and generates a third clock signal in synchronization with the second clock signal, wherein
• the clock generation circuit comprises:
• a delay line that delays a first clock signal to generate the second clock signal;
• a counter circuit that specifies an amount of delay of the delay line based on a count value thereof;
• a counter control circuit that adjusts the count value of the counter circuit so that first active edges of the first and second clock signals have a predetermined relationship;
• and
• a duty adjustment circuit that adjusts a second active edge of the second clock signal based on first and second count values at each of which the first active edges of the first and second clock signals have the predetermined relationship, and wherein
• the counter control circuit updates the count value of the counter circuit so that a first active edge of the third clock signal coincides with the first active edge of the first clock signal, and
• the first and second count values both are count values where the first active edges of the first and third clock signals coincide with each other.

A method of generating a clock signal comprising:

• providing a clock generation circuit that includes a delay line and a counter circuit, the delay line delaying a first clock signal to generate a second clock signal, the counter circuit specifying an amount of delay of the delay line based on a count value thereof;
• acquiring a first count value by adjusting the count value of the counter circuit so that first active edges of the first and second clock signals have a predetermined relationship;
• acquiring a second count value different from the first count value by adjusting the count value of the counter circuit so that the first active edges of the first and second clock signals have the predetermined relationship;
• performing an arithmetic operation using the first and second count values to generate a third count value;
• and
• adjusting a second active edge of the second clock signal based on the third count value.