US 8,299,828 B2Granted

ADPLL circuit, semiconductor device, and portable information device

AssigneeRenesas Electronics Corporation

InventorsRyo Endo, Jiro Shimbo, Tomomitsu Kitamura

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Abstract

The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Claims6

Dependent claims

A method of an ABS (Auto Band Select) operation of an ADPLL (All Digital Phase Lock Loop) including an ABS circuit, a digital phase detector and a digital controlled oscillator, comprising:

(a) inputted an ON signal to the ABS circuit,
(b) outputting a first shift amount of a phase error in beginning of start of the ABS operation between a frequency division signal (DIV) dividing an output of the digital controlled oscillator and a reference signal (REF) from the digital phase detector to the ABS circuit,
(c) storing the first shift amount of the phase error in beginning of start of the ABS operation in a flip-flop of the ABS circuit,
(d) detecting a second shift amount of a phase error between a frequency division signal dividing an output of the digital controlled oscillator and the reference signal (REF) in the digital phase detector after a reference time elapses,
(e) outputting the second shift amount from the digital phase detector to the ABS circuit, and
(f) comparing the first shift amount in the flip-flop with the second shift amount, and detecting a shift direction of a phase error between the first shift amount and the second shift amount in a digital frequency comparator of the ABS circuit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/463,982Filed 4 May 2012 · continuation
Priority: JP 2009-28476516 Dec 2009
Published: US 2012/0212266 A123 Aug 2012
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03L 7/113
For assuring initial synchronisation or for broadening the capture range: using frequency discriminator
H03L 7/099
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop
H03L 7/103
The additional signal being directly applied to the controlled loop oscillator: the additional signal being a digital signal
H03L 2207/06
Indexing scheme relating to automatic control of frequency or phase and to synchronisation: phase locked loops with a controlled oscillator having…

Family

Application12/955,192Parent of this continuation · filed 29 Nov 2010
US 2012/0212266 A1Pre-grant publication · published 23 Aug 2012
US 8,207,767 B2Parent of this continuation
US 2011/0140747 A1Published application
US 8,299,828 B2This patent

From the US filing history. Foreign family members aren’t listed.