High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider

A phase locked loop (PLL) comprising:

• a phase-frequency discriminator (PFD) coupled to receive an input clock and a local clock as inputs, the PFD to generate a comparison output proportional to a phase difference between a phase of the input clock and a phase of the local clock;
• a loop filter coupled to receive the comparison output and to generate a corresponding low-pass filtered signal;
• a voltage controlled oscillator (VCO) coupled to receive the low-pass filtered signal and to generate an intermediate clock, the frequency of the intermediate clock being proportional to the strength of the low-pass filtered signal;
• and
• a first frequency divider to receive the intermediate clock and to divide a frequency of the intermediate clock by a division factor M to generate the local clock, wherein the first frequency divider comprises:
• a least significant (LS) stage designed to divide a frequency of a first input signal by one of the factors two, three or four;
• a plurality of higher significance (HS) stages including a first higher significance stage, each of the plurality of higher significance stages designed to divide a frequency of a corresponding input signal by one of the factors two or three;
• and
• an output stage designed to divide a final input signal either by two or perform no division,
• wherein the first input signal is the intermediate clock, wherein the LS stage is coupled to receive the intermediate clock, and generates a first divided clock and a first output mode signal, a frequency of the first divided clock being less than a frequency of the intermediate clock,
• wherein the first higher significance stage is coupled to receive the first divided clock, and generates a second divided clock, a frequency of the second divided clock being less than the frequency of the first divided clock, and
• wherein the final input signal is the first output mode signal, wherein the output stage is coupled to receive the first output mode signal, and generates the local clock.