Electronic age detection circuit

A circuit comprising:

• a first inverter;
• a second inverter having an input coupled to an output of the first inverter;
• a feedback circuit coupled between an output of the second inverter and the output of the first inverter, wherein the feedback circuit includes an re-channel metal oxide semiconductor (NMOS) transistor having a drive strength greater than a p-channel metal oxide semiconductor (PMOS) transistor of the first inverter;
• and
• a filter having a first node coupled to a supply voltage node, a second node coupled to a ground node, and a third node coupled to an input of the first inverter;
• wherein, responsive to power being applied to the supply voltage node during use, a voltage on the third node rises from and subsequently falls to approximately a voltage of the ground node, and wherein, responsive to the voltage on the third node rising to a level sufficient to change a state of the output of the first inverter, the feedback circuit is configured to activate to overdrive a state of the output of the first inverter and further configured to maintain overdriving the state of the output of the output of the first inverter.

A method comprising:

• initially applying a supply voltage to an electronic circuit;
• providing an input voltage to an input of a first inverter responsive to applying the supply voltage, wherein the input voltage rises and subsequently falls;
• responsive to the input voltage rising to at least a first level:
• changing a state of an output of the first inverter from a first state to a second state;
• changing a state of an output of a second inverter responsive to changing the state of the output of the first inverter;
• activating a feedback transistor responsive to changing the state of the output of the second inverter;
• driving the output of the first inverter back to the first state responsive to activating the feedback transistor;
• and
• maintaining the output of the first inverter at the first state, wherein maintaining the output state comprises the feedback transistor overdriving a transistor of the first inverter, wherein the feedback transistor has a greater drive strength than the transistor of the first inverter.

An integrated circuit comprising:

• a plurality of aging detection circuits, wherein each of the aging detection circuits is configured provide an indication of aging, wherein at least one of the aging detection circuits includes:
• a filter;
• a first inverter having an input coupled to the filter;
• and
• a half-latch having a second inverter and a feedback transistor, wherein the second inverter is coupled in series with the first inverter and wherein the feedback transistor includes a gate terminal coupled to an output of the second inverter and a drain terminal coupled to an output of the first inverter;
• wherein the feedback transistor is configured to, when active, drive the output of the first inverter to a first state;
• and
• a storage unit configured to receive and store indications of aging from each of the plurality of aging circuits;
• wherein the integrated circuit is configured to determine an operating voltage based on reading the indications of aging.

A circuit comprising:

• a filter coupled between a voltage supply node and a ground node;
• a first inverter comprising first and second transistors, wherein an input of the first inverter is coupled to the filter at a first node, and wherein the first transistor is configured to, when active, provide a pull-up path between a second node and the voltage supply node;
• a half-latch circuit comprising a second inverter and a third transistor, wherein an input of the second inverter is coupled to the second node, wherein the second inverter is configured to provide an output on a third node, wherein a gate terminal of the third transistor is coupled to the third node;
• wherein the third transistor is configured to, when active, provide a pull-down path between the second node and the ground node;
• and
• wherein the first and third transistors are sized such that the drive strength of the third transistor exceeds that of the first transistor and such that the second node is pulled down to ground when both the first and third transistors are active.