Integrated gate driver circuit
AssigneeHannstar Display Corp.
InventorsYan Jou Chen, Hsien Cheng Chang
Life of this patent
Estimating the term…
Abstract
An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.
Claims20
An integrated gate driver circuit, receiving a plurality of clock signals and comprising a plurality of cascaded drive units, each drive unit comprising:
- an input terminal;
- an output terminal;
- an output drive circuit, comprising:
- a first switch, comprising a control terminal receiving a first clock signal, a first terminal coupled to the input terminal, and a second terminal coupled to a first node;
- a second switch, comprising a control terminal coupled to the first node, a first terminal receiving a second clock signal, and a second terminal coupled to the output terminal;
- and
- a third switch, comprising a control terminal receiving the first clock signal, a first terminal coupled to the output terminal, and a second terminal coupled to a first voltage;
- and
- a first voltage stabilizing circuit, comprising:
- a fourth switch, comprising a first terminal coupled to a second voltage, a second terminal coupled to a second node, and a control terminal coupled to the first terminal of the fourth switch;
- a fifth switch, comprising a first terminal coupled to the second node, a second terminal coupled to the first voltage, and a control terminal coupled to the output terminal;
- and
- a sixth switch, comprising a first terminal coupled to the output terminal, a second terminal coupled to the first voltage, and a control terminal coupled to the second node.
An integrated gate driver circuit, receiving a plurality of clock signals and comprising a plurality of identical and cascaded drive units, each drive unit comprising:
- an input terminal;
- an output terminal;
- an output drive circuit, comprising:
- a first switch, comprising a control terminal receiving a first clock signal, a first terminal coupled to the input terminal, and a second terminal coupled to a first node;
- a second switch, comprising a control terminal coupled to the first node, a first terminal receiving a second clock signal, and a second terminal coupled to the output terminal;
- and
- a third switch, comprising a control terminal receiving the first clock signal, a first terminal coupled to the output terminal, and second terminal coupled to a voltage source;
- and
- a voltage stabilizing circuit, comprising:
- a tenth switch, comprising a first terminal coupled to the output terminal, a second terminal coupled to the voltage source, and a control terminal coupled to a second node;
- an eleventh switch, comprising a first terminal coupled to the second node, a second terminal coupled to the voltage source, and a control terminal coupled to the first node;
- a twelfth switch, comprising a first terminal coupled to the second node, a second terminal coupled to the first node of an immediately following drive unit, and a control terminal coupled to the second terminal;
- and
- a thirteenth switch, comprising a first terminal coupled to the first node, a second terminal coupled to the voltage source, and a control terminal coupled to the second node.
An integrated gate driver circuit, receiving a plurality of clock signals and comprising a plurality of cascaded drive units, each drive unit comprising:
- an input terminal;
- an output terminal;
- an output drive circuit, comprising;
- a first switch, comprising a control terminal receiving a first clock signal, a first terminal coupled to the input terminal, and a second terminal coupled to a node;
- a second switch, comprising a control terminal coupled to the node, a first terminal receiving a second clock signal, and a second terminal coupled to the output terminal;
- and
- a third switch, comprising a control terminal receiving the first clock signal, a first terminal coupled to the output terminal, and a second terminal coupled to a voltage source;
- and
- a balancing capacitor, coupled to between the node and the control terminal of the third switch.
Dependencies are inferred from the claim text.