US 8,299,819 B2 · Peak or zero current comparator

Abstract

The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Claims8

Dependent claims

A circuit configuration for reducing resettling time of a current detector means, said circuit configuration comprising:

a differential pair of transistors including a first transistor which is coupled between a second node and a third node, wherein said first transistor receives a first input signal of a predetermined value at a first node, and a second transistor which is coupled between said third node and a fifth node, wherein said second transistor receives a second input signal of a variable value at a fourth node, said variable value being able to make a large shift relative to said predetermined value;
a pair of transistors with a polarity different from said differential pair of transistors, including a third transistor which is coupled between said second node and said third node, and a fourth transistor which is coupled between said third node and said fifth node, wherein said third transistor and said fourth transistor share a common input terminal which is connected to said fourth node.

Dependencies are inferred from the claim text.

Peak or zero current comparator

Life of this patent

Peak or zero current comparator

Life of this patent

Abstract

Claims8