Routing layer for mitigating stress in a semiconductor die
AssigneeATI Technologies ULC
InventorsRoden Topacio, Gabriel Wong
Life of this patent
Estimating the term…
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Claims19
A semiconductor die comprising:
- an integrated circuit formed on one surface of a piece of semiconductor wafer;
- a plurality of input-output (I/O) pads interconnected to said integrated circuit;
- a routing layer comprising:
- a dielectric layer formed on said one surface;
- and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads;
- a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps;
- wherein at least one of said UBMs has at least a first one of said conductive traces passing beneath said one of said UBMs and is electrically interconnected to said first conductive trace through said dielectric layer, and wherein at least a second one of said plurality of conductive traces passes proximate said first conductive trace and under said one of said UBMs to mechanically reinforce said routing layer proximate said one of said UBMs.
A semiconductor die, comprising:
- at least one integrated circuit formed on one surface, and a plurality of input-output (I/O) pads connected to said at least one integrated circuit;
- a routing layer comprising a dielectric layer formed on said surface of said die, and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads;
- and
- a plurality of solder bumps formed on said bump-pads, for electrically interconnecting said integrated circuit to a substrate;
- wherein at least one of said conductive traces passes beneath an under-bump metallization (UBM), through a circular area circumscribed by the perimeter of a top surface of said under-bump metallization (UBM) without electrically contacting said UBM, to mechanically reinforce said routing layer proximate said UBM.
A routing layer for a semiconductor die, said routing layer comprising:
- a plurality of conductive traces, each one of said traces extending from a corresponding one of a plurality of input-output (I/O) pads of an integrated circuit formed on a die and electrically interconnected with a corresponding one of a plurality of under bump metallizations (UBMs) through said routing layer;
- at least one of said conductive traces passing proximate one of said UBMs, underneath said one of said UBMs, without electrically contacting said one of said UBMs, to mechanically reinforce said routing layer proximate said one of said UBMs.
A method of manufacturing a semiconductor die for a die having an integrated circuit (IC) interconnected to a plurality of input-output (I/O) pads, said method comprising:
- forming a plurality of conductive traces on a dielectric layer, said traces interconnecting corresponding ones of a plurality of under bump metallization (UBM) contact points and said I/O pads, at least one of said conductive traces passing proximate one of said contact points and under a UBM corresponding to said one of said contact points so as to reinforce said dielectric layer proximate said one of said UBM contact points;
- and
- attaching a plurality of solder bumps, each to a UBM interconnected with a corresponding one of said UBM contact points.
Dependencies are inferred from the claim text.