Semiconductor package
AssigneeShinko Electric Industries Co., Ltd.
InventorsMasahiro Sunohara, Yuichi Taguchi
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. The semiconductor device includes a semiconductor substrate and a penetration electrode penetrating the semiconductor substrate. A cavity part is formed in the semiconductor substrate to isolate the penetration electrode from the semiconductor substrate. A connection terminal is provided at a position where the connection terminal does not overlap the penetration electrode in a plan view. The connection terminal electrically connects the semiconductor device to the wiring board.
Claims8
A semiconductor package comprising:
- a wiring board;
- and
- a semiconductor device mounted on said wiring board,
- wherein said semiconductor device includes:
- a semiconductor substrate;
- a penetration electrode penetrating said semiconductor substrate;
- a cavity part formed in said semiconductor substrate to surround and isolate said penetration electrode from said semiconductor substrate;
- a first wiring formed on a front surface of said semiconductor substrate, the first wiring extending over said cavity part and connected to said penetration electrode;
- and
- a second wiring formed on a back surface of said semiconductor substrate, the second wiring extending over said cavity part and connected to said penetration electrode,
- wherein, in a plan view of said semiconductor substrate, said first wiring and said second wiring do not overlap each other in a portion corresponding to said cavity part.
A semiconductor package comprising:
- a wiring board;
- a rewiring substrate;
- and
- a semiconductor device mounted on said wiring board by way of said rewiring substrate,
- wherein said rewiring substrate includes:
- a substrate;
- a penetration electrode penetrating said substrate;
- a cavity part formed in said substrate to isolate said penetration electrode from said substrate;
- a first wiring formed on a front surface of said semiconductor substrate, the first wiring extending over said cavity part and connected to said penetration electrode;
- and
- a second wiring formed on a back surface of said semiconductor substrate, the second wiring extending over said cavity part and connected to said penetration electrode,
- wherein, in a plan view of said semiconductor substrate, said first wiring and said second wiring do not overlap each other in a portion corresponding to said cavity part.
Dependencies are inferred from the claim text.