Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules

A semiconductor wafer structure configured with heat dissipating carbon nanotubes prior to semiconductor device and metallization layer formation, said semiconductor wafer structure comprising:

• a semiconductor wafer having a back side and a front side opposite said back side;
• a diffusion barrier layer immediately adjacent to and covering said semiconductor wafer on said back side;
• a blanket catalyst layer immediately adjacent to and covering said diffusion barrier layer;
• a spacer layer adjacent to said catalyst layer;
• trenches extending vertically through said spacer layer to said blanket catalyst layer;
• a plurality of clusters of carbon nanotubes within said trenches, each one of said trenches containing a single protected cluster of carbon nanotubes adjacent to a portion of said blanket catalyst layer at a bottom surface of said one of said trenches;
• and
• a dielectric protective cap layer immediately adjacent to said spacer layer and covering all of said trenches,
• said trenches and said dielectric protective cap layer protecting said clusters of carbon nanotubes during subsequent formation, on said front side, of semiconductor devices and metallization layers for discrete integrated circuit chips, and
• said clusters of carbon nanotubes being adapted to provide enhanced thermal dissipation during subsequent operation of said discrete integrated circuit chips.

A semiconductor wafer structure configured with heat dissipating carbon nanotubes prior to semiconductor device and metallization layer formation, said semiconductor wafer structure comprising:

• a semiconductor wafer having a back side and a front side opposite said back side;
• trenches extending vertically into said semiconductor wafer on said back side;
• diffusion barrier layers lining said trenches;
• catalyst layers on horizontal surfaces only of said diffusion barrier layers;
• a plurality of clusters of carbon nanotubes within said trenches, each one of said trenches containing a single protected cluster of carbon nanotubes adjacent to a catalyst layer within said one of said trenches;
• and
• a dielectric protective cap layer immediately adjacent to said semiconductor wafer on said back side and covering all of said trenches,
• said trenches and said dielectric protective cap layer protecting said clusters of carbon nanotubes during subsequent formation, on said front side, of semiconductor devices and metallization layers for discrete integrated circuit chips, and
• said clusters of carbon nanotubes being adapted to provide enhanced thermal dissipation during subsequent operation of said discrete integrated circuit chips.