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US 8,299,580 B2Granted
Semiconductor wafer and a method of separating the same
AssigneePanasonic Corporation
InventorsTakahiro Kumakawa, Hideki Kojima, Tomoaki Furukawa
Life of this patent
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Abstract
A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines.
Claims11
A semiconductor wafer, where a plurality of predetermined separation lines are provided, comprising:
- a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines, wherein:
- a first stress applying layer is formed on an upper surface of the semiconductor substrate so as to be disposed on both sides of each of the predetermined separation lines, said first stress applying layer having an opening above each of said predetermined separation lines, said first stress applying layer applying compressive stress to the semiconductor substrate which is in contact with the first stress applying layer,
- a circuit formation layer is formed on the semiconductor substrate in each of the chip regions, and
- the first stress applying layer is provided from a top surface of the circuit formation layer to a top surface of the semiconductor substrate.
1 more element
A method of separating a semiconductor wafer comprising the steps of:
- (a) preparing a wafer;
- in which a plurality of predetermined separation lines are provided, which includes a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines, and in which tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines;
- (b) irradiating with laser light, an inside of the semiconductor substrate along the predetermined separation lines to form a plurality of modified regions in a depth direction;
- and
- (c) separating the semiconductor substrate into the individual chip regions along cracks generated from the modified regions,
- wherein the semiconductor wafer includes a first stress applying layer formed on an upper surface or a back surface of the semiconductor substrate and on both sides of the predetermined separation lines including a space, and applying compressive stress to the semiconductor substrate, which is in contact with the first stress applying layer,
- a circuit formation layer is formed on the semiconductor substrate in each of the chip regions, and
- the first stress applying layer is provided from a top surface of the circuit formation layer to a top surface of the semiconductor substrate.
5 more elements
Dependencies are inferred from the claim text.