Through wafer vias and method of making same
AssigneeInternational Business Machines Corporation
InventorsHanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
Life of this patent
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Abstract
A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
Claims11
A structure, comprising:
- a semiconductor substrate having a top surface and an opposite bottom surface;
- and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of said array of through wafer vias extending from said top surface of said substrate to said bottom surface of said substrate;
- wherein said at least one electrically conductive through wafer via comprises a first trench filled only with an electrical conductor;
- and
- wherein said at least one electrically non-conductive through wafer via comprises a second trench having a filling only consisting of a dielectric liner extending to the top surface of said substrate that surrounds an electrically conductive core and a dielectric plug at one end of said second trench.
A method, comprising:
- forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of said array of through wafer vias extending from said top surface of said substrate to said bottom surface of said substrate;
- wherein said at least one electrically conductive through wafer via comprises a first trench filled only with an electrical conductor;
- and
- wherein said at least one electrically non-conductive through wafer via comprises a second trench having a filling only consisting of a dielectric liner extending to the top surface of said substrate that surrounds an electrically conductive core and a dielectric plug at one end of said second trench.
A signal transmission line through a semiconductor substrate, said substrate having a top surface and an opposite bottom surface, comprising:
- a conductive through wafer via extending from said top surface of said substrate to said bottom surface of said substrate, sidewalls of said conductive through wafer via in physical and electrical contact with said substrate;
- and a non-conductive through wafer via extending from said top surface of said substrate to said bottom surface of said substrate, said non-conductive through wafer via proximate to and separated from said conductive through wafer via by a region of said substrate;
- wherein said conductive through wafer via comprises a first trench filled only with an electrical conductor;
- and
- wherein said non-conductive through wafer via comprises a second trench having a filling only consisting of a dielectric liner extending to the to surface of said substrate that surrounds an electrically conductive core and a dielectric plug at one end of said second trench.
Dependencies are inferred from the claim text.