Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates

A method of forming a field effect transistor, said method comprising:

• forming an isolation region in a semiconductor layer so as to form a semiconductor body laterally surrounded by said isolation region,
• said semiconductor body having a bottom surface, a top surface, and opposing sides and opposing ends extending vertically from said top surface to said bottom surface, said opposing sides comprising a first side and a second side opposite said first side and said opposing ends comprising a first end and a second end opposite said first end,
• said semiconductor body having, by design, a designated source region at said first end, a designated channel region positioned laterally adjacent to said designated source region, a designated drain drift region positioned laterally adjacent to said designated channel region and a designated drain region at said second end positioned laterally adjacent to said designated drain region;
• and
• forming a gate structure such that said gate structure traverses said top surface of said semiconductor body from said first side to said second side above said designated channel region and such that said gate structure comprises extensions adjacent to said designated drain drift region in said semiconductor body,
• said extensions being on said first side and said second side,
• each extension extending vertically through said isolation region and extending laterally from said designated channel region toward said designated drain region, and
• each extension further having a sidewall that is angled relative to said semiconductor body such that a portion of said isolation region between said extension and said semiconductor body has a continuously increasing width along a length of said designated drain drift region from said designated channel region to said designated drain region.

A field effect transistor comprising:

• a semiconductor body having a first side and a second side opposite said first side, said semiconductor body comprising:
• a channel region;
• a drain drift region positioned laterally adjacent to said channel region;
• and
• a drain region positioned laterally adjacent to said drain drift region opposite said channel region;
• an isolation region positioned laterally around said semiconductor body;
• a gate structure comprising extensions adjacent to said drain drift region on said first side and said second side,
• each extension extending vertically through said isolation region and extending laterally from said channel region toward said drain region, and
• each extension further having a sidewall that is angled relative to said semiconductor body such that a portion of said isolation region between said extension and said semiconductor body has a continuously increasing width along a length of said drain drift region from said channel region to said drain region;
• a substrate;
• and
• an insulator layer on said substrate, said semiconductor body and said isolation region being on said insulator layer and said extensions extending vertically through said isolation region to said insulator layer.

A field effect transistor comprising:

• a semiconductor body having a first side and a second side opposite said first side, said semiconductor body comprising:
• a channel region;
• a drain drift region positioned laterally adjacent to said channel region;
• and
• a drain region positioned laterally adjacent to said drain drift region opposite said channel region;
• an isolation region positioned laterally around said semiconductor body;
• and
• a gate structure comprising extensions adjacent to said drain drift region on said first side and said second side,
• each extension extending vertically through said isolation region and extending laterally from said channel region toward said drain region, and
• each extension further having a sidewall that is angled relative to said semiconductor body such that a portion of said isolation region between said extension and said semiconductor body has a continuously increasing width along a length of said drain drift region from said channel region to said drain region,
• said semiconductor body further comprising:
• a source region;
• and
• a plurality of semiconductor fingers extending from said source region to said drain region, each semiconductor finger comprising
• a corresponding channel region;
• and
• a corresponding drain drift region positioned laterally between said corresponding channel region and said drain region, and
• said gate structure further comprising a shared extension positioned between each pair of adjacent semiconductor fingers.

A method of forming a field effect transistor, said method comprising:

• forming an isolation region in a semiconductor layer so as to form a semiconductor body laterally surrounded by said isolation region, said semiconductor body having a first side and a second side opposite said first side;
• forming a gate structure such that said gate structure comprises extensions adjacent to a designated drain drift region in said semiconductor body,
• said designated drain drift region being positioned laterally between said designated channel region and a designated drain region in said semiconductor body,
• said extensions being on said first side and said second side,
• each extension extending vertically through said isolation region and extending laterally from said designated channel region toward said designated drain region, and
• each extension further having a sidewall that is angled relative to said semiconductor body such that a portion of said isolation region between said extension and said semiconductor body has a continuously increasing width along a length of said designated drain drift region from said designated channel region to said designated drain region;
• and
• before said forming of said isolation region, providing a semiconductor-on-insulator wafer comprising a substrate, an insulator layer on said substrate and said semiconductor layer on said insulator layer,
• said forming of said gate structure comprising forming said gate structure such that said extensions extend vertically through said isolation region to said insulator layer.