Semiconductor devices with vertical extensions for lateral scaling

A method for forming a CMOS semiconductor device comprising:

• providing a semiconductor substrate doped with a first conductivity dopant in a first device region and doped with a second conductivity dopant in a second device region;
• forming a first mask on the second device region, wherein the first device region exposed;
• forming second conductivity raised extension regions on a first portion of the semiconductor substrate in the first device region, said second conductivity raised extension regions have a first concentration of second conductivity dopant;
• forming second conductivity raised source regions and second conductivity raised drain regions on the second conductivity raised extension regions, wherein the second conductivity raised source regions and the second conductivity raised drain regions each have a second concentration of the second conductivity dopant that is greater than the first concentration of the second conductivity dopant in the second conductivity raised extension regions, wherein an inner edge of the second conductivity raised source regions and the second conductivity raised drain regions is aligned to an inner edge of the second conductivity raised extension regions;
• removing the first mask and forming a second mask on the first device region leaving the second device region exposed;
• forming first conductivity raised extension regions on a first portion of the semiconductor substrate in the second device region, said first conductivity raised extension regions have a third concentration of first conductivity dopant;
• forming first conductivity raised source regions and first conductivity raised drain regions on the first conductivity raised extension regions, the first conductivity raised source regions and the first conductivity raised drain regions each having a fourth concentration of the first conductivity dopant that is greater than the third concentration of first conductivity dopant in the first conductivity raised extension regions, wherein an inner edge of the first conductivity raised source regions and the first conductivity raised drain regions is aligned to an inner edge of the first conductivity raised extension regions;
• and
• forming gate structures on second portions of the semiconductor substrate that are between the first portion of the semiconductor substrate in the first device region and the second device region.

A semiconductor device comprising:

• a semiconductor substrate including at least one surface having a first conductivity type;
• a gate structure present on the at least one surface of the semiconductor substrate,
• wherein the gate structure includes a gate dielectric layer that is positioned between the semiconductor substrate and a base of a gate conductor, wherein the gate dielectric layer is also present on sidewalls of the gate conductor;
• raised extension regions of a second conductivity type present on a portion of the semiconductor substrate that is adjacent to the gate structure, wherein the raised extension regions have a first dopant concentration, wherein an inner edge of the raised extension regions contacts the gate dielectric layer that is present on the sidewalls of the gate conductor;
• and
• raised source regions and raised drain regions of a second conductivity type present on the raised extension regions, wherein the raised source regions and raised drain regions have a second dopant concentration that is greater than the first dopant concentration, wherein an inner edge of the raised source regions and the raised drain regions is aligned with the inner edge of the raised extension regions.