US 8,299,545 B2Granted

Method and structure to improve body effect and junction capacitance

AssigneesInternational Business Machines Corporation, Freescale Semiconductor, Inc.

InventorsXiangdong Chen, Geng Wang, Da Zhang

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Abstract

A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

Claims11

Dependent claims

A transistor structure comprising:

a substrate comprising a top surface;
a channel region within said substrate adjacent said top surface, said channel region comprising a first-type impurity within said substrate;
a gate stack on said top surface of said substrate, said gate stack being positioned above said channel region;
source and drain regions within said substrate adjacent said top surface, said channel region being positioned between said source and drain regions, said source and drain regions comprising a second-type impurity within said substrate, said second-type impurity having an opposite polarity with respect to said first-type impurity;
a primary body doping region within said substrate below, relative to said top surface, said channel region, said primary body doping region being positioned between said source and drain regions within each said transistor structure, and said primary body doping region comprising a greater concentration of said first-type impurity relative to a concentration of said first-type impurity within said channel region;
and
secondary body doping regions within said substrate below, relative to said top surface, said source and drain regions, said secondary body doping regions comprising a greater concentration of said first type impurity relative to a concentration of said first-type impurity within said channel region,
said secondary body doping regions being positioned at a greater depth below said top surface of said substrate than said primary body doping region.

5 more elements

A transistor structure comprising:

a substrate comprising a top surface;
a channel region within said substrate adjacent said top surface, said channel region comprising a first-type impurity within said substrate;
a gate stack on said top surface of said substrate, said gate stack being positioned above said channel region;
source and drain regions within said substrate adjacent said top surface, said channel region being positioned between said source and drain regions, said source and drain regions comprising a second-type impurity within said substrate, said second-type impurity having an opposite polarity with respect to said first-type impurity;
a primary body doping region within said substrate below, relative to said top surface, said channel region, said primary body doping region being positioned between said source and drain regions within each said transistor structure, and said primary body doping region comprising a greater concentration of said first-type impurity relative to a concentration of said first-type impurity within said channel region;
and
secondary body doping regions within said substrate below, relative to said top surface, said source and drain regions, said secondary body doping regions comprising a greater concentration of said first type impurity relative to a concentration of said first-type impurity within said channel region,
said secondary body doping regions being separated from said primary body doping region by a portion of said substrate, and
said secondary body doping regions being positioned at a greater depth below said top surface of said substrate than said primary body doping region.

6 more elements

A transistor structure comprising:

a substrate comprising a top surface;
a channel region within said substrate adjacent said top surface, said channel region comprising a first-type impurity within said substrate;
a gate stack on said top surface of said substrate, said gate stack being positioned above said channel region;
source and drain regions within said substrate adjacent said top surface, said channel region being positioned between said source and drain regions, said source and drain regions comprising a second-type impurity within said substrate, said second-type impurity having an opposite polarity with respect to said first-type impurity;
a primary body doping region within said substrate below, relative to said top surface, said channel region, said primary body doping region being positioned between said source and drain regions within each said transistor structure, and said primary body doping region comprising a greater concentration of said first-type impurity relative to a concentration of said first-type impurity within said channel region;
and
secondary body doping regions within said substrate below, relative to said top surface, said source and drain regions, said secondary body doping regions comprising a greater concentration of said first type impurity relative to a concentration of said first-type impurity within said channel region,
said secondary body doping regions being positioned at a greater depth below said top surface of said substrate than said primary body doping region, and
said greater depth corresponding to an amount said gate stack extends above said top surface of said substrate.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/695,565Filed 28 Jan 2010
Published: US 2011/0180883 A128 Jul 2011
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation