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US 8,299,542 B2Granted
MOSFET with multiple fully silicided gate and method for making the same
AssigneeInternational Business Machines Corporation
InventorsZhijiong Luo, Huilong Zhu
Life of this patent
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Abstract
A field-effect transistor is provided. The field-effect transistor includes a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric, and the upper region has a second lateral dimension different from the first lateral dimension.
Claims7
A field-effect transistor comprising:
- a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric;
- the upper region comprises a top region and a middle region having different outer most lateral dimensions,
- wherein the top region has an uppermost lateral dimension in accordance with the lateral dimension of the gate dielectric and a lowermost lateral dimension at an interface with the middle region in accordance with the lateral dimension of the gate dielectric, and the middle region has a lateral dimension greater than the first lateral dimension;
- and
- the top region is of a first silicide material and the middle region and lower region are of a second silicide material different from the first silicide material, and wherein sidewalls of said lower region and at least a portion of a bottom surface of said middle region are in direct contact with a layer of insulating material.
2 more elements
A field-effect transistor comprising:
- a gate including a gate dielectric overlying a substrate, and a multiple fully silicided gate structure overlying the gate dielectric,
- having a top region of a first silicide material and having an uppermost width in accordance with a width of the crate dielectric and a lowermost width in accordance with the width of the crate dielectric,
- a middle region of a second silicide material and having a width greater than the uppermost and lowermost widths of the top region,
- the top region overlying the middle region and in contact therewith, and a lower region of the second silicide material contiguous with the middle region and having a width in accordance with the width of the gate dielectric, wherein the first silicide material is different from the second silicide material.
1 more element
Dependencies are inferred from the claim text.