US 8,299,538 B2 · Differential nitride pullback to create differential NFET to PFET divots for improved performance versus leakage

Abstract

Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.

Claims15

Dependent claims

An integrated circuit structure comprising:

a substrate;
a first transistor on said substrate, said first transistor comprising:
a first semiconductor body having a first sidewall;
and
a first isolation region adjacent to said first sidewall, said first isolation region having a first divot positioned laterally immediately adjacent to a first upper portion of said first sidewall;
and
a second transistor on said substrate, said second transistor comprising:
a second semiconductor body having a second sidewall;
and
a second isolation region adjacent to said second sidewall, said second isolation region having a second divot positioned laterally immediately adjacent to a second upper portion of said second sidewall, said second divot having a greater depth than said first divot.

7 more elements

An integrated circuit structure comprising:

a substrate;
a logic circuit on said substrate, said logic circuit comprising:
a first transistor, having a first conductivity type, on said substrate, said first transistor comprising:
a first semiconductor body having a first sidewall;
and
a first isolation region adjacent to said first sidewall, said first isolation region having a first divot positioned laterally immediately adjacent to a first upper portion of said first sidewall;
and
a second transistor, having a second conductivity type different from said first conductivity type, on said substrate, said second transistor comprising:
a second semiconductor body having a second sidewall;
and
a second isolation region adjacent to said second sidewall, said second isolation region having a second divot positioned laterally immediately adjacent to a second upper portion of said second sidewall, said second divot having a greater depth than said first divot;
and
a plurality of analog devices on said substrate, said analog devices comprising:
a third transistor, having said first conductivity type, on said substrate, said third transistor comprising:
a third semiconductor body having a third sidewall;
and
a third isolation region adjacent to said third sidewall, said third isolation region having one of a third divot and no divot positioned laterally immediately adjacent to a third upper portion of said third sidewall;
and
a fourth transistor, having said second conductivity type, on said substrate, said fourth transistor comprising:
a fourth semiconductor body having a fourth sidewall;
a fourth isolation region adjacent to said fourth sidewall, said fourth isolation region having one of a fourth divot and no divot positioned laterally immediately adjacent to a fourth upper portion of said fourth sidewall,
said second divot having a greater depth than said third divot, when said third isolation region has said third divot positioned laterally immediately adjacent to said third upper portion of said third sidewall,
said second divot having a greater depth than said fourth divot, when said fourth isolation region has said fourth divot positioned laterally immediately adjacent to said fourth upper portion of said fourth sidewall, and
any divots in said first isolation region, said third isolation region and said fourth isolation region having approximately equal depths.

21 more elements

An integrated circuit structure comprising:

a substrate;
a logic circuit on said substrate, said logic circuit comprising:
a first transistor, having a first conductivity type, on said substrate, said first transistor comprising:
a first semiconductor body having a first sidewall;
and
a first isolation region adjacent to said first sidewall, said first isolation region having a first divot positioned laterally immediately adjacent to a first upper portion of said first sidewall;
and
a second transistor, having a second conductivity type different from said first conductivity type, on said substrate, said second transistor comprising:
a second semiconductor body having a second sidewall;
and
a second isolation region adjacent to said second sidewall, said second isolation region having a second divot positioned laterally immediately adjacent to a second upper portion of said second sidewall, said second divot having a greater depth than said first divot;
and
a memory circuit on said substrate, said memory circuit comprising:
a fifth transistor, having said first conductivity type, on said substrate, said fifth transistor comprising:
a fifth semiconductor body having a fifth sidewall;
and
a fifth isolation region adjacent to said fifth lower portion, said fifth isolation region having a fifth divot adjacent to a fifth upper portion of said fifth sidewall;
and
a sixth transistor, having said second conductivity type, on said substrate, said sixth transistor comprising:
a sixth semiconductor body having a sixth sidewall;
and
a sixth isolation region adjacent to said sixth sidewall, said sixth isolation region having a sixth divot adjacent to a sixth upper portion of said sixth sidewall, said sixth divot, said fifth divot and said second divot having approximately equal depths.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/859,903Filed 20 Aug 2010 · division

Priority

4 Jun 2008

Published

US 2010/0314688 A116 Dec 2010

Granted

30 Oct 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions

Family

Application12/132,798Parent of this division · filed 4 Jun 2008

US 7,838,355 B2Parent of this division · filed 23 Nov 2010

US 2010/0314688 A1Pre-grant publication · published 16 Dec 2010

US 2009/0302374 A1Published application

US 8,299,538 B2This patent

From the US filing history. Foreign family members aren’t listed.

Differential nitride pullback to create differential NFET to PFET divots for improved performance versus leakage

Life of this patent

Differential nitride pullback to create differential NFET to PFET divots for improved performance versus leakage

Life of this patent

Abstract

Claims15