Delta monolayer dopants epitaxy for embedded source/drain silicide

A semiconductor structure comprising:

• at least one pFET gate stack and at least one nFET gate stack located on an upper surface of a semiconductor substrate, each of the at least one pFET gate stack and the at least one nFET gate stack includes a source extension region and a drain extension region located within the semiconductor substrate at a footprint of both the at least one pFET gate stack and the at least one nFET gate stack, and a device channel located between the source extension region and the drain extension region and beneath each of the gate stacks;
• pFET embedded stressor elements located on opposite sides of the at least one pFET gate stack and within the semiconductor substrate, and nFET embedded stressor elements located on opposite sides of the at least one nFET gate stack and within the semiconductor substrate, wherein each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, wherein the first layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the second layer of the second epitaxy doped semiconductor material, and a monolayer of dopant located on an upper surface of the second layer of each of the embedded stressor elements;
• and
• a metal semiconductor alloy located on an upper surface of the delta monolayer of dopant.

A method of fabricating a structure comprising:

• forming at least one FET gate stack on an upper surface of a semiconductor substrate;
• forming a source extension region and a drain extension region within the semiconductor substrate at the footprint of the at least one FET gate stack;
• forming recessed regions on opposite sides of the at least one FET gate stack and within the semiconductor substrate;
• forming pre-embedded stressor elements substantially within the recessed regions, wherein each of the pre-embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, wherein the first layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the second layer of the second epitaxy doped semiconductor material, a delta monolayer of dopant located on an upper surface of the second layer, and a third layer of epitaxy doped semiconductor layer located atop the delta monolayer;
• and
• converting a portion of the third layer of the pre-embedded stressor element into a metal semiconductor alloy contact, wherein said metal semiconductor alloy contact is located directly an upper surface of the delta monolayer.