Vertical NPNP structure in a triple well CMOS process

A method of fabricating a device structure, the method comprising:

• forming, in first active region of a p-type bulk substrate, an NPNP structure containing a first n-type semiconductor region, a first p-type semiconductor region, and a second n-type semiconductor region that are arranged in depth to define a first vertical NPN bipolar transistor and a first vertical PNP bipolar transistor, the p-type semiconductor region shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor, and the second n-type semiconductor region shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor;
• forming a first wiring path in an interconnect structure and connected to the first n-type semiconductor region and the p-type semiconductor region of the NPNP structure;
• forming an I/O pad connected by the first wiring path to the first n-type semiconductor region and the p-type semiconductor region of the NPNP structure;
• and
• forming a second wiring path in the interconnect structure configured to connect the second n-type semiconductor region and the p-type semiconductor region of the NPNP structure to a positive power supply voltage.

A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an electrostatic discharge (ESD) protection device including a first region of n-type semiconductor material, a second region of n-type semiconductor material, a first region of p-type semiconductor material, a second region of p-type semiconductor material, and an input/output (I/O) pad electrically connected to the first region of n-type semiconductor material and the first region of p-type semiconductor material, the first region of p-type semiconductor material stacked vertically between the first and second regions of n-type semiconductor material to form a vertical NPN bipolar transistor, the first and second regions of p-type semiconductor material stacked vertically relative to the second region of n-type semiconductor material to form a vertical PNP bipolar transistor, the first region of p-type semiconductor material shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor, the second region of n-type semiconductor material shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor, and the second region of n-type semiconductor material and the second region of p-type semiconductor material configured to be electrically connected to a positive power supply voltage such that an electrostatic discharge (ESD) pulse of negative voltage at the I/O pad is directed through the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor to a power supply supplying the positive power supply voltage.