Structure and method to fabricate pFETS with superior GIDL by localizing workfunction

A method of forming a semiconductor structure comprising:

• forming at least one patterned gate stack within a pFET device region of a semiconductor substrate;
• forming extension regions within said semiconductor substrate at a footprint of the at least one patterned gate stack, wherein said extension regions define a channel region located beneath the at least one patterned gate stack;
• introducing a workfunction tuning species by angled ion implantation into a portion of at least one of said extension regions that is located adjacent to the channel region of the at least one patterned gate stack and into at least one sidewall portion of the at least one patterned gate stack;
• and
• forming a spacer on said semiconductor substrate with said pFET device region, said spacer having an inner edge in contact with a vertical sidewall of said at least one patterned gate stack in said pFET device region and an opposing outer edge.

A method of forming a semiconductor structure comprising:

• forming at least one patterned gate stack within a pFET device region of a semiconductor substrate and at least one patterned gate stack within an nFET device region of said semiconductor structure;
• forming extension regions within said semiconductor substrate at a footprint of the at least one patterned gate stack within said pFET device region, wherein said extension regions define a channel region located beneath the at least one patterned gate stack within said pFET device region;
• and
• introducing a workfunction tuning species by only an anneal process comprising an atmosphere containing said workfunction tuning species into a portion of at least one of said extension regions that is located adjacent to the channel region of the at least one patterned gate stack within said pFET device region and into at least one sidewall portion of the at least one patterned gate stack within said pFET device region, wherein said at least one patterned gate stack within said nFET device region is protected during said introducing said workfunction tuning species.