Power IC device and method for manufacturing same

A power IC device comprising:

• a surface layer channel CMOS transistor and a trench power MOS transistor which are formed on a same chip,
• the trench power MOS transistor including,
• a gate region embedded in a trench,
• an inversion channel region formed on a sidewall of the trench,
• a single source region formed above the gate region and the inversion channel region, the source region having a thickness that is about uniform, with a continuous, flat, non-disjointed bottom surface,
• a drain electrode formed over an entire back surface layer of the chip,
• wherein:
• the source region of the trench power MOS transistor and a gate electrode of the surface layer channel CMOS transistor are formed in a same layer.

A power IC device comprising:

• a surface layer channel CMOS transistor and a trench power MOS transistor which are formed on a same chip,
• said surface layer channel CMOS transistor including:
• an inversion channel region formed in a part of a surface layer of the chip, in which part no trench is formed, so as to be in parallel with the surface layer;
• and
• a gate electrode formed on the inversion channel region,
• said trench power MOS transistor including:
• a gate region embedded in the trench, which is formed in a part of the surface layer of the chip;
• an inversion channel region formed on a sidewall of the trench;
• a single source region formed above the gate region and the inversion channel region, the source region having a thickness that is about uniform, with a continuous, flat, non-disjointed bottom surface;
• and
• a drain electrode formed over an entire back surface layer of the chip,
• the source region of the trench power MOS transistor and the gate electrode of the surface layer channel CMOS transistor being formed in a same layer.

A method for manufacturing a power IC device, the method comprising:

• forming a surface layer channel CMOS transistor and a trench power MOS transistor in a same wafer,
• the trench power MOS transistor including,
• a gate region embedded in a trench,
• an inversion channel region formed on a sidewall of the trench,
• a single source region formed above the gate region and the inversion channel region, the source region having a thickness that is about uniform, with a continuous, flat, non-disjointed bottom surface;
• the forming of the transistors including forming a gate electrode of the surface layer channel CMOS transistor and forming a source region of the trench power MOS transistor in a same step;
• and
• forming a drain electrode over and an entire back surface of the wafer.

A method for manufacturing a power IC device, the method comprising:

• forming a surface layer channel CMOS transistor and a trench power MOS transistor in a same wafer,
• the forming of the surface layer channel CMOS transistor including forming an inversion channel region in a part of a surface layer of the wafer, in which part no trench is formed, so as to be in parallel with the surface layer,
• the forming of the trench power MOS transistor including forming a trench in a part of a surface layer of the wafer, embedding a gate region in the trench, and forming an inversion channel region on a sidewall of the trench,
• the forming of the surface layer channel CMOS transistor including forming gate electrode on the inversion channel region;
• forming a single source region above the gate region and the inversion channel region of the trench power MOS transistor, and forming a gate electrode of the surface layer channel CMOS transistor, in a same step,
• the source region having a thickness that is about uniform, with a continuous, flat, non-disjointed bottom surface;
• and
• forming a drain electrode over an entire back surface of the wafer.