Semiconductor device employing transistor having recessed channel region and method of fabricating the same

A recess channel transistor comprising:

• a semiconductor substrate having an active region;
• a trench within the active region, the trench including an upper trench region adjacent to a surface of the active region and having a lower boundary located at a first corner of inner walls of the trench and oriented in a plane substantially parallel with the surface of the active region, a lower trench region having an upper boundary located at a second corner of the inner walls of the trench structure and oriented in a plane substantially parallel with the surface of the active region, and a buffer trench region interposed between the lower boundary of the upper trench region and the upper boundary of the lower trench region, wherein a width of the lower trench region is greater than a width of the upper trench region and wherein the inner walls of the trench structure are curved throughout the lower trench region and throughout the buffer trench region;
• a gate electrode in the trench;
• a gate dielectric layer in the trench between the gate electrode and the inner wall of the trench;
• and
• source and drain regions in the active region on respective opposite sides of the trench and directly adjacent the trench.

A recess channel transistor comprising:

• a semiconductor substrate having a first surface and an active region;
• a trench extending from the first surface into the semiconductor substrate within the active region, the trench including an upper trench region adjacent to the first surface of the semiconductor substrate and having a lower boundary located at a first corner of sidewalls of the trench and oriented in a first plane substantially parallel with the first surface of the semiconductor substrate, a lower trench region having an upper boundary located at a second corner of the sidewalls of the trench structure and oriented in a second plane substantially parallel with the first surface of the semiconductor substrate, and a buffer trench region interposed between the lower boundary of the upper trench region and the upper boundary of the lower trench region, wherein a sidewall of the trench in the upper trench region extends along a plane that is substantially perpendicular to the first surface of the semiconductor substrate, and the sidewall of the trench in the buffer trench region is curved,
• wherein a width of the lower trench region is greater than a width of the upper trench region,
• the sidewalls of the trench in the buffer trench region at the first corner curve away from the sidewalls of the trench at the upper trench region at respective angles substantially less than 90 degrees so that a width of the buffer trench region is greater than a width of the upper trench region;
• a gate electrode in the trench;
• a gate dielectric layer in the trench between the gate electrode and the inner wall of the trench;
• and
• source and drain regions in the active region on respective opposite sides of the trench and directly adjacent the trench.