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US 8,299,506 B2Granted
Integration of MEMS and CMOS devices on a chip
AssigneeHoneywell International Inc.
InventorsAndy Peczalski, Robert E. Higashi, Gordon Alan Shaw, Thomas Keyser
Life of this patent
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Abstract
A method of forming CMOS circuitry integrated with MEMS devices includes bonding a wafer to a top surface layer having contacts formed to CMOS circuitry. A handle wafer is then removed from one of the top or bottom surfaces of the CMOS circuitry, and MEMS devices are formed in a remaining silicon layer.
Claims12
A semiconductor chip comprising:
- a CMOS circuit supported by a first wafer comprising a first silicon on insulator layer a first silica layer;
- and
- a second wafer, comprising a second silicon on insulator layer and a second silica layer, bonded to the first wafer on the side of the first wafer supporting the CMOS circuit, wherein a portion of the first or second wafer is removed to expose a MEMS formation layer separated from the CMOS circuit by at least one silicon on insulator layer;
- and wherein at least one of the first or second wafers has a handle wafer.
1 more element
A semiconductor chip comprising:
- a first CMOS circuit in a CMOS layer having a first contact extending to a first silicon on insulator layer of a first wafer, the first wafer including a first silica layer;
- a second CMOS circuit in the CMOS layer having a second contact extending to a second silicon on insulator layer of the first wafer, wherein the second silicon on insulator layer and first silicon on insulator layers are separated by an insulating layer;
- an adhesion layer supported by the CMOS layer;
- a second wafer, including a third silicon on insulation layer and a second silica layer, bonded to the adhesion layer of the first wafer, wherein a portion of the first or second wafer is removed to expose a MEMS formation layer separated from the first CMOS circuit by at least one silicon on insulator layer;
- and wherein at least one of the first or second wafers has a handle wafer.
2 more elements
A semiconductor chip comprising:
- a CMOS circuit supported by a first wafer comprising a first silicon on insulator layer and a first silica layer;
- and
- a second wafer, comprising a second silicon on insulator layer and a second silica layer, bonded to the first wafer on the side of the first wafer supporting the CMOS circuit, wherein at least one of the first or second wafers has a handle wafer, removal of which will expose a MEMS formation layer separated from the CMOS circuit by at least one silicon on insulator layer.
Dependencies are inferred from the claim text.