Memory cell for modification of revision identifier in an integrated circuit chip

In an integrated circuit chip including a plurality of metal layers and first and second supply potentials, a memory cell for storing a revision number of said integrated circuit chip, said memory cell comprising:

• a first metal interconnect structure and a second metal interconnect structure that traverse a plurality of metal layers and arranged to form a stacked structure comprising first and second alternating metal interconnect patterns;
• and
• outputs coupled to said first and second supply potentials by said first and second metal interconnect structures, physically arranged and configured to output a revision number of said integrated circuit chip,
• wherein said first and second supply potentials comprise buses configured and physically arranged to be accessible at each of said metal layers;
• and
• wherein said first and second interconnect structures and said first and second supply potentials are physically arranged and configured to store a value in said memory cell.

In an integrated circuit chip including a plurality of metal layers and first and second supply potentials, a programmable memory cell for storing a value, said memory cell comprising:

• a first metal interconnect structure and a second metal interconnect structure;
• and
• an output coupled to at least one of said first and second supply potentials by at least one of said first and second metal interconnect structures;
• wherein said first and second supply potentials comprise buses configured and physically arranged to be accessible at each of said metal layers;
• and
• wherein said first and second interconnect structures and said first and second supply potentials are physically arranged and configured to store a value in said memory cell.