Field effect transistor
AssigneeRenesas Electronics Corporation
InventorsMasayuki Aoike, Yasunori Bito
Life of this patent
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Abstract
A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer; and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.
Claims12
A field effect transistor comprising:
- a Schottky layer;
- a stopper layer formed of InGaP and provided in a recess region on said Schottky layer;
- a cap layer provided on said stopper layer and formed of GaAs;
- and
- a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between said stopper layer and said cap layer,
- wherein said cap layer comprises:
- a high concentration cap layer;
- and
- a low concentration cap layer having an impurity provided directly or indirectly under said high concentration cap layer and having an impurity concentration lower than said high concentration cap layer,
- wherein said barrier rising suppression region is provided for a layer between said stopper layer and said low concentration cap layer, and comprises a GaAs electron compensation layer which contains said impurity of a higher concentration than said low concentration cap layer.
A field effect transistor comprising:
- a Schottky layer;
- a stopper layer (9) formed of InGaP and provided in a recess region (20) on said Schottky layer;
- a cap layer (11, 12) provided on said stopper layer and formed of GaAs;
- and
- a barrier rising suppression region (10) comprised of a Si-doped GaAs carrier compensation layer provided in the recess region (20) on said Schottky layer, the Si-doped GaAs carrier compensation layer located between said stopper layer (9) and said cap layer (11, 12), the barrier rising suppression region (10) configured to suppress rising of a potential barrier due to interface charge between said stopper layer and said cap layer,
- wherein said cap layer comprises:
- a high concentration cap layer (12);
- and
- a low concentration cap layer (11) provided directly or indirectly under said high concentration cap layer and having an impurity concentration lower than said high concentration cap layer and lower than said Si-doped GaAs carrier compensation layer.
Dependencies are inferred from the claim text.