Active pixel sensor with nanowire structured photodetectors

#This application is related to U.S. application Ser. No. 12/621,497, filed Nov. 19, 2009, entitled “NANOWIRE CORE-SHELL LIGHT PIPES,” which is incorporated herein in its entirety by reference.

#The present invention relates generally to the field of semiconductor imaging devices which can be fabricated using standard CMOS processes plus a nanowire fabrication process.

#Imaging devices implemented in complementary metal oxide semiconductor (CMOS) are well known and widely used together with CCD image sensors. CMOS imaging devices have a number of advantages: (1) they can reduce the cost and power consumption, (2) they are easy to manufacture, employing the highly standardized process developed for massive production of consumer integrated circuits (ICs) including memory chips and microprocessors and other digital and analog ICs, and (3) they integrate multiple functions on a single chip, allowing the scaling down of the size and power consumption of the device. They also allow for the adoption of smaller geometry processes provided by new advancements in the CMOS process.

#Embodiments of the present disclosure will now be disclosed, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts.

#FIG. 1 illustrates a cross sectional view of a prior art small CMOS pixel.

#FIG. 2a illustrates a simplified cross sectional view of an embodiment of a pixel with a nanowire structured photodetector with front side illumination.

#In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. In the drawings, similar symbols typically identify similar components, unless the context dictates otherwise. The illustrative embodiments described in the detail description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.

#Symbols for elements illustrated in the figures are summarized in the following table. The elements are described in more detail below.

#TABLE 1 Symbol Element VPG 1 (VP Gate 1) The first vertical photogate VPG 2 (VP Gate 1) The second vertical photogate TX Gate Transfer gate RG Reset gate RD Reset drain Sub substrate Out Output NW (nw) Nanowire PG photogate I (i) Current n+, n− Semiconducting material with excess donors, n+ is heavily doped, n− is lightly doped p+, p− Semiconducting material with excess acceptors, p+ is heavily doped, p− is lightly doped