Test structure for charged particle beam inspection and method for defect determination using the same
AssigneeHermes Microvision, Inc.
InventorHong Xiao
Life of this patent
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Abstract
A test structure and method thereof for determining a defect in a sample of semiconductor device includes at least one transistor rendered grounded. The grounded transistor is preferably located at least one end of a test pattern designed to be included in the sample. When the test structure is inspected by charged particle beam inspection, the voltage contrast (VC) of the transistors in the test pattern including the grounded transistor is observed for determination of the presence of defect in the sample.
Claims29
A method for determining a defect in a sample of semiconductor device, comprising:
- providing said sample with at least one test row of transistors, wherein at least one transistor in each said test row of transistor is rendered grounded;
- obtaining a charged particle microscopic image of said sample;
- and
- determining said defect in said sample by monitoring the voltage contrast (VC) level of said test rows of transistors from said charged particle microscopic image,
- wherein said grounded transistor is rendered grounded by allowing electrical conduction between a doped region of said grounded transistor and a substrate,
- wherein said allowing electrical conduction between said doped region and said substrate is achieved by a shorter doped region between said doped region and said substrate.
A test structure for determining a defect of a semiconductor device, comprising:
- at least one test row of transistors, at least one transistor in each said test row of transistors being rendered grounded,
- wherein said defect is determined by monitoring the voltage contrast (VC) level of said test rows of transistors from a charged particle microscopic image of said sample,
- wherein said grounded transistor is rendered grounded by allowing electrical conduction between a doped region of said grounded transistor and a substrate,
- wherein said allowing electrical conduction between said doped region and said substrate is achieved by a shorter doped region between said doped region and said substrate.
A test structure for detecting a sub-threshold leakage defect, comprising:
- at least one test row of transistors;
- and
- a shorter doped region under at least one transistor in each said test row of transistor, the shorter doped region having the same conductive type to a source of the at least one transistor, such that the source is grounded to a substrate through the shorter doped region.
A method for forming a test structure with a source-to-substrate short, said method comprising steps of:
- providing a substrate with a first conductive type;
- forming a first well of the first conductivity type within the substrate by using a first mask, wherein the first mask has a covered region;
- forming a second well of a second conductivity type within the substrate by using a second mask, wherein the second mask has an un-covered region superimposed to the covered region, such that a shorter doped region is formed within the substrate, the second conductivity type being opposed to the first conductivity type;
- and
- forming a plurality of transistors in and on the substrate, wherein the shorter doped region is beneath one source of the plurality of transistors, such that a source-to-substrate short is created.
A method for testing a sub-threshold leakage defect, comprising steps of:
- providing a test structure with at least one test row of transistors, and a doped region under at least one transistor in each said test row of transistor, wherein the doped region has the same conductive type to a source of the at least one transistor, such that the source is grounded;
- and
- scanning the test structure by using an E-beam inspection tool, wherein a contact electrically connecting to the source will exhibit the sub-threshold leakage defect.
Dependencies are inferred from the claim text.