US 8,299,453 B2Granted

CMOS transistors with silicon germanium channel and dual embedded stressors

AssigneeInternational Business Machines Corporation

InventorHuilong Zhu

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Abstract

A p-type MOSFET of a CMOS structure has a silicon-germanium alloy channel to which a longitudinal compressive stress is applied by embedded epitaxial silicon-germanium alloy source and drain regions comprising a silicon-germanium alloy having a higher concentration of germanium than the channel of the p-type MOSFET. An n-type MOSFET of the CMOS structure has a silicon-germanium alloy channel to which a longitudinal tensile stress is applied by embedded epitaxial silicon source and drain regions comprising silicon. The silicon-germanium alloy channel in the p-type MOSFET provides enhanced hole mobility, while the silicon-germanium alloy channel in the n-type MOSFET provides enhanced electron mobility, thereby providing performance improvement to both the p-type MOSFET and the n-type MOSFET.

Claims14

Dependent claims

A semiconductor structure comprising a field effect transistor located on a semiconductor substrate, wherein said field effect transistor comprises:

a body region including a channel-containing body portion having a doping of a first conductivity type and comprising a silicon-germanium alloy having a first atomic concentration of germanium and including a channel;
a source region having a doping of a second conductivity type and comprising a silicon-germanium alloy having a second atomic concentration of germanium, wherein said second atomic concentration is greater than said first atomic concentration, and wherein said second conductivity type is the opposite of said first conductivity type;
and
a drain region having a doping of said second conductivity type and comprising a silicon-germanium alloy having said second atomic concentration of germanium, wherein said body region further includes:
a source-side body portion comprising intrinsic epitaxial silicon and being substantially free of germanium;
and
a drain-side body portion comprising intrinsic epitaxial silicon and being substantially free of germanium.

4 more elements

A semiconductor structure comprising a first field effect transistor and a second field effect transistor located on a semiconductor substrate,

wherein said first field effect transistor comprises:
a first body region including a first channel-containing body portion having a doping of a first conductivity type and comprising a silicon-germanium alloy having a first atomic concentration of germanium and including a first channel;
a first source region having a doping of a second conductivity type and comprising a silicon-germanium alloy having a second atomic concentration of germanium, wherein said second atomic concentration is greater than said first atomic concentration, and wherein said second conductivity type is the opposite of said first conductivity type;
and
a first drain region having a doping of said second conductivity type and comprising a silicon-germanium alloy having said second atomic concentration of germanium,
and wherein said second field effect transistor comprises:
a second body region including a second channel-containing body portion having a doping of second conductivity type and comprising a silicon-germanium alloy having said first atomic concentration of germanium and including a second channel;
a second source region having a doping of said first conductivity type and comprising silicon and being substantially free of germanium;
and
a second drain region having a doping of first conductivity type and comprising silicon and being substantially free of germanium.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/699,225Filed 3 Feb 2010 · us provisional application
Priority: 3 Mar 2009
Published: US 2010/0224938 A19 Sep 2010
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 30/0278
Of lateral single-gate IGFETs: forming single crystalline channels on wafers after forming insulating device isolations
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/751
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions