US 8,298,963 B2Granted

Semiconductor device and manufacturing method of the same

AssigneeRenesas Electronics Corporation

InventorsToshihiko Akiba, Minoru Kimura, Masao Odagiri

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Abstract

With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can be diced without damaging a relatively fragile low-k layer.

Claims16

Dependent claims

A manufacturing method of a semiconductor device comprising the steps of:

(a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface opposed to the main surface;
(b) in the dicing region of the semiconductor wafer, inserting a first dicing blade into the semiconductor wafer from the main surface side to the back surface side of the semiconductor wafer, and forming a dicing groove in the main surface of the semiconductor wafer by causing the first dicing blade to run along the dicing region;
(c) after the step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer, and separating the semiconductor wafer into a plurality of semiconductor chips by causing the second dicing blade to run along the dicing region;
(d) disposing the semiconductor chips obtained by performing the step (c) over a chip mounting portion of a chip mounting substrate;
(e) after the step (d), electrically coupling the semiconductor chips to the chip mounting substrate, respectively;
and
(f) sealing the semiconductor chip with a resin,
wherein the semiconductor wafer has a base material layer, a semiconductor element layer formed over the base material layer, a first interconnect layer formed over the semiconductor element layer, and a second interconnect layer formed over the first interconnect layer,
wherein the dielectric constant of a first insulating layer placed in the first interconnect layer is lower than the dielectric constant of each of a premetal insulating layer formed in the semiconductor element layer and a second insulating layer placed in the second interconnect layer,
wherein the first dicing blade used in the step (b) has a circular planar shape,
wherein the cross-sectional shape of the first dicing blade at the circumferential portion thereof has a first side face, a second side face having a first side-face angle of inclination relative to the first side face, and a third side face having relative to the first side face a second side-face angle of inclination greater than the first side-face angle of inclination,
wherein the width between second boundary points of the second side face and the third side face is smaller than the width between first boundary points of the first side face and the second side face, and
wherein in the step (b), the first dicing blade is inserted into the semiconductor wafer such that the second boundary points of the first dicing blade reach the base material layer.

10 more elements

A manufacturing method of a semiconductor device comprising the steps of:

(a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface opposed to the main surface;
(b) in the dicing region of the semiconductor wafer, inserting a first dicing blade into the semiconductor wafer from the main surface side to the back surface side of the semiconductor wafer, and forming a dicing groove in the main surface of the semiconductor wafer by causing the first dicing blade to run along the dicing region;
(c) after the step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer, and separating the semiconductor wafer into a plurality of semiconductor chips by causing the second dicing blade to run along the dicing region;
(d) disposing the semiconductor chips obtained by performing the step (c) over a chip mounting portion of a chip mounting substrate;
(e) after the step (d), electrically coupling the semiconductor chips to the chip mounting substrate, respectively;
and
(f) sealing the semiconductor chip with a resin,
wherein the semiconductor wafer has a base material layer, a semiconductor element layer formed over the base material layer, a first interconnect layer formed over the semiconductor element layer, and a second interconnect layer formed over the first interconnect layer,
wherein the dielectric constant of a first insulating layer placed in the first interconnect layer is lower than the dielectric constant of each of a premetal insulating layer formed in the semiconductor element layer and a second insulating layer placed in the second interconnect layer,
wherein the first dicing blade used in the step (b) has a circular planar shape,
wherein the cross-sectional shape of the first dicing blade at the circumferential portion thereof has a first face and a second face having a first side-face angle of inclination relative to the first face, and
wherein in the step (b), the first dicing blade is caused to run along the dicing region such that the first interconnect layer is brought into contact with the second face of the first dicing blade.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/690,733Filed 20 Jan 2010
Priority: JP 2009-01157022 Jan 2009
Published: US 2010/0181681 A122 Jul 2010
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10P 54/00
Cutting or separating of wafers, substrates or parts of devices
B28D 5/022
By rotary tools, e.g. drills: by cutting with discs or wheels
H10D 62/117
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes of semiconductor bodies
H10W 74/114
The semiconductor body being completely enclosed: by a substrate and the encapsulations