US 8,298,934 B2Granted

Structure and method of creating entirely self-aligned metallic contacts

AssigneeInternational Business Machines Corporation

InventorsJeffery B. Maxson, Cung Do Tran, Huilong Zhu

Life of this patent

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Abstract

The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

Claims10

Dependent claims

A method of forming a semiconductor structure comprising:

providing a patterned material stack comprising a lower layer of polysilicon and an upper layer of polysilicon germanium on a surface of a semiconductor substrate, said patterned material stack having sidewalls that are covered by at least one spacer;
removing said upper layer of polysilicon germanium from said patterned material stack;
forming a first metal semiconductor alloy layer within said polysilicon layer and forming a second metal semiconductor alloy layer within said semiconductor substrate at a footprint of said at least one spacer;
forming a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re on, and self-aligned to said first metal semiconductor alloy layer;
and
forming a second first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re on, and self-aligned to said second metal semiconductor alloy layer, wherein said forming said first and second metallic contacts are performed simultaneously or in separate steps.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/155,056Filed 7 Jun 2011 · division
Priority: 7 Jan 2008
Published: US 2011/0237067 A129 Sep 2011
Granted: 30 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/0131
The conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of…: the…
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Family

Application11/970,165Parent of this division · filed 7 Jan 2008
US 2011/0237067 A1Pre-grant publication · published 29 Sep 2011
US 7,964,923 B2Parent of this division
US 2009/0174006 A1Published application
US 8,298,934 B2This patent

From the US filing history. Foreign family members aren’t listed.