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US 8,298,932 B2Granted
Vertical interconnect structure, memory device and associated production method
AssigneeInfineon Technologies AG
InventorsMartin Gutsche, Franz Kreupl, Harald Seidl
Life of this patent
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Abstract
The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
Claims13
A method for producing a memory device comprising the steps of:
- forming a multiplicity of insular active regions in a semiconductor substrate,
- forming two strip-type word line stacks with a gate dielectric layer and a gate layer on the semiconductor substrate in such a way that three contact regions are formed in the insular active regions,
- forming a common drain region in a contact region lying between the two word line stacks and forming source regions in the remaining contact regions,
- forming a common nanoelement on the common drain region, and forming additional nanoelements on the source regions,
- embedding the common nanoelement in a dielectric layer,
- forming a first depression in the dielectric layer in the region of the common nanoelement,
- filling a bit line layer into the first depression, the bit line layer being electrically connected to the contact region lying between the two word stacks,
- etching the bit line layer back to form a second depression,
- filling completely the second depression with a dielectric filling material, and
- forming at least one memory element at the surface of the dielectric layer in such a way that it is electrically connected to the additional nanoelements.
7 more elements
A method for producing a memory device comprising the steps of:
- forming a multiplicity of insular active regions in a semiconductor substrate,
- forming two strip-type word line stacks with a gate dielectric layer and a gate layer on the semiconductor substrate in such a way that three contact regions are formed in the insular active regions,
- forming a common drain region in a contact region lying between the two word line stacks and forming source regions in the remaining contact regions,
- forming nanoelements on the source regions,
- forming a dielectric layer over the common drain region and the nanoelements,
- etching back the dielectric layer to uncover an upper region of the nanoelements;
- forming a dielectric etching stop layer at the surface of the dielectric layer and of the uncovered regions of the nanoelements;
- forming an auxiliary dielectric layer at the surface of the etching stop layer;
- forming a trench in the region of the common drain region in the dielectric layer, the etching stop layer and the auxiliary dielectric layer as far as the drain region, filling a bit line layer into the trench, etching the bit line layer back to form a depression, and
- filling completely the depression with dielectric filling material.
7 more elements
Dependencies are inferred from the claim text.