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US 8,298,930 B2Granted
Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
AssigneeInternational Business Machines Corporation
InventorsCharles L. Arvin, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
Life of this patent
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Abstract
A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.
Claims19
A method of making a semiconductor structure, comprising:
- forming an upper level wiring layer composed of an electrical insulator material;
- forming a wire in the upper level wiring layer;
- forming a plurality of capping layers on the wire and the upper level wiring layer;
- forming a passivation layer on the plurality of capping layers;
- forming a first barrier layer metallurgy (BLM) layer on and contacting a bond pad in a chip, wherein the bond pad is formed in the passivation layer, over the wire, and extending through the plurality of capping layers toward the wire;
- forming a second BLM layer on and contacting the first BLM layer;
- forming a solder material on and contacting the second BLM layer, wherein the first and second BLM layers extend laterally outward relative to side edges of the solder material;
- removing portions of the second BLM layer such that the second BLM layer is aligned with the side edges of the solder material;
- patterning the first BLM layer, wherein the patterning forms an undercut beneath the solder material;
- forming a repair material in the undercut and on the solder material;
- removing the repair material from the solder material;
- and
- reflowing the solder material.
10 more elements
A method of forming a semiconductor structure, comprising:
- forming an upper level wiring layer composed of an electrical insulator material;
- forming a wire in the upper level wiring layer;
- forming a plurality of capping layers on the wire and the upper level wiring layer;
- forming a passivation layer on the plurality of capping layers;
- forming a final via in the passivation layer to expose an upper surface of a bond pad, wherein the bond pad is formed in the passivation layer, over the wire, and extending through the plurality of capping layers toward the wire;
- forming a first barrier layer metallurgy (BLM) layer on and contacting the upper surface of the bond pad in a chip;
- forming a second BLM layer on the first BLM layer;
- forming a photoresist on an upper surface of the second BLM layer, wherein the photoresist has an opening over the final via and the photoresist is formed after the second BLM layer;
- forming a solder bump on and contacting the upper surface of the second BLM layer and within the opening of the photoresist;
- patterning the first and second BLM layers, wherein the patterning forms an undercut at an edge of the solder bump by over-etching the first BLM layer, and wherein the patterning etches the second BLM layer to an edge of the solder bump;
- conformally depositing a repair material on the first and second BLM layers and the solder bump, wherein the depositing substantially fills the undercut with the repair material;
- patterning the repair material to remove the repair material from a surface of the solder bump while leaving the repair material in the undercut;
- and
- reflowing the solder bump to form a solder ball.
11 more elements
A semiconductor structure, comprising:
- a barrier layer metallurgy (BLM) formed in a final via and contacting a bond pad in a chip;
- a solder material on the BLM, wherein an edge of the BLM is recessed laterally inward relative to an edge of the solder material;
- a repair material filling a region between the edge of the BLM and the edge of the solder material;
- an upper level wiring layer composed of an electrical insulator material;
- a wire formed in the upper level wiring layer;
- a plurality of capping layers formed on the wire and the upper level wiring layer;
- and
- a passivation layer formed on the plurality of capping layers,
- wherein the bond pad is formed in the passivation layer, over the wire, and extending through the plurality of capping layers toward the wire;
- the BLM comprises at least one copper-containing layer and at least one TiW-containing layer;
- the solder material comprises tin;
- and
- the repair material is substantially non-reactive with the tin and comprises one of:
- gamma-aminopropyltriethoxysilane, hexamethyldisilazane, Ni, and SiO2.
11 more elements
Dependencies are inferred from the claim text.