Method for differential spacer removal by wet chemical etch process and device with differential spacer structure
AssigneeAdvanced Micro Devices, Inc.
InventorsMaciej Wiatr, Frank Wirbeleit, Andy Wei, Andreas Gehring
Life of this patent
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Abstract
By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.
Claims13
A method for differential spacer removal, comprising:
- depositing an etch stop layer over a semiconductor microstructure including at least an NMOS element and a PMOS element, each of said NMOS element and said PMOS element comprising a plurality of spacer elements, wherein each plurality of spacer elements comprises an outer spacer element, and the etch stop layer contacts and covers said outer spacer elements of said pluralities of spacer elements;
- implanting N-dopants through the previously deposited etch stop layer;
- removing a first portion of said etch stop layer covering said outer spacer element of said at least one NMOS element while leaving a second portion of said etch stop layer in place over said outer spacer element of said at least one PMOS element;
- and
- removing at least said outer spacer element from a sidewall of said at least one NMOS element after removing said first portion by performing a wet chemical etch process, while said outer spacer element of said PMOS element is protected from the wet chemical etch process by the etch stop layer.
A method for differential spacer removal from a semiconductor microstructure with an NMOS and a PMOS transistor, each of which comprise a plurality of spacer elements, the method comprising:
- depositing an etch stop layer over the semiconductor microstructure, wherein the etch stop layer covers an outer spacer element of each of the pluralities of spacer elements;
- implanting N-dopants through the etch stop layer;
- removing a first portion of said etch stop layer covering said outer spacer element of said NMOS transistor by performing a dry etch process while leaving a second portion of said etch stop layer in place over said outer spacer element of said PMOS transistor;
- removing at least said outer spacer element from a sidewall of said NMOS transistor after removing said first portion by performing a wet chemical etch process;
- and
- depositing a stressed capping layer on the semiconductor microstructure.
Dependencies are inferred from the claim text.