US 8,298,914 B2Granted

3D integrated circuit device fabrication using interface wafer as permanent carrier

AssigneeInternational Business Machines Corporation

InventorsMukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu

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Abstract

A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.

Claims10

Dependent claims

A method for fabricating a 3D integrated circuit, the method comprising the steps of:

providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;
providing a first active circuitry layer wafer including active circuitry and through-silicon vias;
bonding the first active circuitry layer wafer face down to the interface wafer;
after bonding the first active circuitry layer wafer face down to the interface wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer;
after removing the first portion of the first active circuitry layer wafer, fabricating a second wiring layer on the second portion of the first active circuitry layer wafer;
providing a second active circuitry layer wafer including active circuitry;
bonding the second active circuitry layer wafer face down to the second wiring layer;
after bonding the second active circuitry layer wafer face down to the second wiring layer, removing a first portion of the second active circuitry layer wafer such that a second portion of the second active circuitry layer wafer remains attached to the second wring layer;
after removing the first portion of the second active circuitry layer wafer, fabricating a third wiring layer on the second portion the second active circuitry layer wafer;
providing a base wafer, the base wafer including a fourth wiring layer;
bonding the third wiring layer face down to the base wafer;
after bonding the third wiring layer face down to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer;
and
bonding the solder bumps to a package.

11 more elements

A method for fabricating a 3D integrated circuit structure, the method comprising the steps of:

providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;
providing a first active circuitry layer wafer including active circuitry;
bonding the first active circuitry layer wafer face down to the interface wafer;
after bonding the first active circuitry layer wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer;
providing a base wafer, the base wafer including a second wiring layer;
bonding a stack structure face down to the base wafer, the stack structure including the interface wafer and the second portion of the first active circuitry layer wafer;
and
after bonding the stack structure, thinning the interface wafer so as to form an interface layer, and forming metallizations on the interface layer, the metallizations being coupled through the through-silicon vias in the interface layer to the first wiring layer.

5 more elements

Dependencies are inferred from the claim text.