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US 8,298,906 B2Granted
Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch
AssigneeInternational Business Machines Corporation
InventorsKerry Bernstein, Francis Roger White
Life of this patent
Estimating the term…
Abstract
A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.
Claims24
A method of forming a semiconductor structure, comprising:
- etching a via trench and a capacitor trench in a wafer in a single RIE process, wherein:
- the via trench has a first depth which avoids effects of RIE lag, and
- the capacitor trench has a second depth less than the first depth due to the effects of RIE lag;
- forming a liner of insulator material on exposed surfaces of the via trench and the capacitor trench;
- filling the via trench and the capacitor trench with a conductor over the liner;
- and
- grinding a backside of the wafer and the liner in the via trench to expose at least the conductor in the via trench without exposing the liner or the conductor in the capacitor trench.
4 more elements
A method for forming a semiconductor structure, comprising:
- forming a hard mask on an upper surface of a substrate;
- forming a first opening in the hard mask, the first opening having a first dimension;
- forming a second opening in the hard mask, the second opening having a second dimension smaller than the first dimension;
- substantially simultaneously etching a first trench of a first depth and a second trench of a second depth in the substrate through the first opening and the second opening, respectively,
- wherein RIE lag limits the second depth of the second trench to less than the first depth of the first trench, and forms the second trench with a vertical upper portion, a tapered lower portion, and a rounded bottom portion;
- forming materials within the first trench and the second trench;
- and
- grinding a backside of the substrate to expose the materials in the first trench without exposing the materials in the second trench.
5 more elements
A method for fabricating a through silicon via and a trench capacitor in a wafer, comprising:
- etching a via trench and a capacitor trench in the wafer at a same time using a same RIE process, wherein:
- a first dimension of the via trench is of a first size such that a depth of the via trench is substantially unaffected by RIE lag during the etching;
- a second dimension of the capacitor trench is of a second size such that a depth of the capacitor trench is limited by RIE lag during the etching;
- forming a liner of insulator material on exposed surfaces of the via trench and the capacitor trench;
- filling the via trench and the capacitor trench with a same conductive material in a same deposition process;
- and
- grinding a backside of the wafer to expose the liner and conductor in the via trench without exposing the liner or the conductor in the capacitor trench.
4 more elements
Dependencies are inferred from the claim text.