Method for manufacturing semiconductor device having multi-layered contact
AssigneeHynix Semiconductor Inc.
InventorJung Nam Kim
Life of this patent
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Abstract
A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.
Claims15
A method for manufacturing a semiconductor device comprising:
- forming a buried gate in a cell region on a substrate;
- forming a gate pattern including a planar channel in a core and peripheral region;
- forming a multi-layered contact and a multi-layered line in the core and peripheral region, the multi-layered contact including a first contact and a second contact provided over the first contact, the multi-layered line including a first line and a second line, the first line provided between the first and the second contacts;
- and
- coupling the first line formed over the first contact that has substantially the same height as that of the gate pattern to a bit line of the cell region.
A method for manufacturing a semiconductor device comprising:
- forming a buried gate in a cell region;
- forming a gate pattern including a planar channel in a core and peripheral region;
- forming a lower contact in the core and peripheral region;
- forming a bit line and a storage node contact in the cell region;
- forming an upper contact over the lower contact;
- and
- forming a storage node over the storage node contact.
A method for manufacturing a semiconductor device comprising:
- forming a cell gate in a cell region of a substrate;
- forming a peri gate in a peripheral region of the substrate;
- forming a first insulating layer over the cell gate and the peri gate, the first insulating layer being substantially planar;
- and
- patterning the first insulating layer to form a bit line in the cell region and a lower metal wire pattern in the peripheral region, wherein the bit line is coupled to the substrate at a first side of the cell gate, and the lower metal wire pattern is coupled to the peri gate, the substrate at a first side of the peri gate, or the substrate at a second side of the peri gate,
- wherein the bit line includes a conductive pattern and a hard mask pattern formed over the conductive pattern.
Dependencies are inferred from the claim text.