Process of forming an electronic device including a trench and a conductive structure therein

A process of forming an electronic device comprising:

• providing a workpiece including a first layer, a well region, a well contact region, a source region, a buried doped region, and a gate electrode, wherein:
• the first layer has a primary surface;
• the well region lies adjacent to the primary surface;
• the well contact region lies adjacent to the primary surface and within the well region and has a higher peak doping concentration as compared to the well region;
• the source region lies adjacent to the primary surface and within the well region and has a higher peak doping concentration as compared to the well region;
• the buried doped region is spaced apart from the primary surface and the well region;
• the gate electrode overlies the first layer and the well region;
• the first layer, the source region, and the buried doped region have a first conductivity type;
• and
• the well region and the well contact region have a second conductivity type opposite that of the first conductivity type;
• etching a trench extending to the buried doped region, wherein portions of the first layer and the well region lie along a sidewall of the trench;
• implanting a dopant into first layer along the sidewall of the trench;
• depositing an insulating layer into the trench;
• anisotropically etching the insulating layer to form a sidewall spacer along the sidewall of the trench;
• depositing a conductive layer to fill a remaining portion of the trench;
• polishing the conductive layer to form a conductive structure, wherein:
• polishing removes a portion of the conductive layer that overlies the source region and the gate electrode;
• and
• the sidewall spacer lies between the conductive structure and the sidewall of the trench;
• and
• forming a first interconnect, a second interconnect, and a third interconnect, wherein:
• the first interconnect is electrically connected to the conductive structure;
• the second interconnect is electrically connected to the well contact region and the source region;
• and
• the third interconnect is electrically connected to the gate electrode.

A process of forming an electronic device comprising:

• providing a workpiece including a first layer, a well region, and a buried doped region, wherein:
• the first layer has a primary surface;
• the well region lies adjacent to the primary surface;
• and
• the buried doped region is spaced apart from the primary surface and the well region;
• forming a gate electrode that overlies the well region and the first layer at the primary surface;
• forming a source region within the well region and adjacent to the primary surface;
• forming a well contact region within the well region and adjacent to the primary surface, wherein the well contact region has a higher peak dopant concentration as compared to the well region;
• forming a trench extending towards the buried doped region, wherein a portion of the first layer lies along a sidewall of the trench, and wherein forming the trench is performed after forming the gate electrode;
• doping the portion of the first layer along the sidewall of the trench to form a sidewall doped region, wherein:
• dopant for the sidewall doped region is introduced into the first layer along the sidewall of the trench;
• doping is performed after forming the trench;
• and
• the sidewall doped region is spaced apart from the buried doped region;
• and
• forming a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region.