Method to reduce threshold voltage variability with through gate well implant

A method of forming a semiconductor device comprising:

• forming an isolation region through a semiconductor layer of a substrate, wherein the isolation region defines a device region of the substrate;
• forming a gate conductor having a first portion over a channel portion of the semiconductor layer in the device region of the substrate and a second portion over the isolation regions, wherein a first upper surface of the first portion of the gate conductor is separated from the upper surface of the channel portion of the semiconductor layer by a first distance, and a second upper surface of the second portion of the gate conductor is separated from the upper surface of the isolation regions by a second distance, the first distance being greater than the second distance;
• implanting a first dopant through the gate conductor into the channel portion of the semiconductor layer, wherein the peak concentration of the first dopant is in a first channel implant region that extends from a lower portion of the gate conductor to an upper portion of the semiconductor layer;
• and
• implanting a second dopant through the gate conductor into the channel portion of the semiconductor layer, wherein the peak concentration of the second dopant is in a second channel implant region that is present in the lower portion of the semiconductor layer.