Array substrate and method for manufacturing the array substrate
AssigneeSamsung Electronics Co., Ltd.
InventorsShin-Il Choi, Sang-Gab Kim, Yu-Gwang Jeong, Hong-Kee Chin
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AssigneeSamsung Electronics Co., Ltd.
InventorsShin-Il Choi, Sang-Gab Kim, Yu-Gwang Jeong, Hong-Kee Chin
Estimating the term…
An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
A method for manufacturing an array substrate, the method comprising:
Dependencies are inferred from the claim text.